Minimizing the dissipated power of RF transceivers is the primarily target to meet the requirements of wearable wireless sensor networks (W-WSN). This paper presents an Ultra-Low Power (ULP) receiver with RF performance exceeding the requirements of the intended application. Thanks to the highly efficient current-reuse Low Noise Amplifier (LNA), followed by a passive mixer, the single-ended 2.4 GHz RF input is down-converted to a low-IF. To generate 25% quadrature LO signals, a high-swing complementary current-reuse Class-C VCO, operating at twice the desired frequency, is followed by a frequency divider-by-two. Furthermore, complex channel selection filtering with center frequency and passband of 2 MHz and 1 MHz respectively is performed utilizing the Gm-boosted Common-Gate baseband stage immediately following the mixer. The proposed receiver is designed and simulated in 40 nm CMOS technology. The entire receiver consumes only 220 μW from 0.8 V supply voltage. It shows DSB-NF of 7.5 dB, conversion gain of 50 dB and image rejection of 20 dB. The proposed design represents almost two times better power efficiency with respect to the state-of-the-art with better or equal RF performance.
A Sub-1V, 220 μw Receiver Frontend for Wearable Wireless Sensor Network Applications
Kargaran E.;Manstretta D.;Castello R.
2018-01-01
Abstract
Minimizing the dissipated power of RF transceivers is the primarily target to meet the requirements of wearable wireless sensor networks (W-WSN). This paper presents an Ultra-Low Power (ULP) receiver with RF performance exceeding the requirements of the intended application. Thanks to the highly efficient current-reuse Low Noise Amplifier (LNA), followed by a passive mixer, the single-ended 2.4 GHz RF input is down-converted to a low-IF. To generate 25% quadrature LO signals, a high-swing complementary current-reuse Class-C VCO, operating at twice the desired frequency, is followed by a frequency divider-by-two. Furthermore, complex channel selection filtering with center frequency and passband of 2 MHz and 1 MHz respectively is performed utilizing the Gm-boosted Common-Gate baseband stage immediately following the mixer. The proposed receiver is designed and simulated in 40 nm CMOS technology. The entire receiver consumes only 220 μW from 0.8 V supply voltage. It shows DSB-NF of 7.5 dB, conversion gain of 50 dB and image rejection of 20 dB. The proposed design represents almost two times better power efficiency with respect to the state-of-the-art with better or equal RF performance.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
