This paper gives a quantitative analysis of the main mechanisms setting fundamental limits to the linearity performances of CMOS direct down-conversion mixers. An advanced low voltage solution is proposed for 3G cell-phones in a 90 nm CMOS technology that achieves: 3nV/radicHz average input referred noise in the band from 10 kHz to 1.92 MHz, a flicker noise corner of 300 kHz, 9 dBm IIP3 and 75 dBm minimum IIP2 while drawing 5.4 mA from a 1.2 V supply.
High Linearity Down-Conversion CMOS Mixers
MANSTRETTA, DANILO
2008-01-01
Abstract
This paper gives a quantitative analysis of the main mechanisms setting fundamental limits to the linearity performances of CMOS direct down-conversion mixers. An advanced low voltage solution is proposed for 3G cell-phones in a 90 nm CMOS technology that achieves: 3nV/radicHz average input referred noise in the band from 10 kHz to 1.92 MHz, a flicker noise corner of 300 kHz, 9 dBm IIP3 and 75 dBm minimum IIP2 while drawing 5.4 mA from a 1.2 V supply.File in questo prodotto:
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