A high performance all digital PLL RF synthesizer is presented. The key building block is a high resolution time to digital converter (TDC) that allows for low in-band phase noise. The TDC uses a novel architecture that combines a simple analog circuitry with a digital control loop to achieve a PVT stable sub-gate delay quantization step, with small area and low power consumption. A prototype of the TDC integrated in 0.13mum CMOS shows 12ps resolution with 1 and 1.15 LSB of DNL and INL respectively. A complete 2GHz ADPLL test chip has been then integrated and measured showing an in-band phase noise of -102dBc and maximum in-band spurs of -42dBc while consuming 15mW
A 3MHz Bandwidth Low Noise RF All Digital PLL with 12ps Resolution Time to Digital Converter
CASTELLO, RINALDO
2006-01-01
Abstract
A high performance all digital PLL RF synthesizer is presented. The key building block is a high resolution time to digital converter (TDC) that allows for low in-band phase noise. The TDC uses a novel architecture that combines a simple analog circuitry with a digital control loop to achieve a PVT stable sub-gate delay quantization step, with small area and low power consumption. A prototype of the TDC integrated in 0.13mum CMOS shows 12ps resolution with 1 and 1.15 LSB of DNL and INL respectively. A complete 2GHz ADPLL test chip has been then integrated and measured showing an in-band phase noise of -102dBc and maximum in-band spurs of -42dBc while consuming 15mWI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
