A PRML read/write IC operating up to 450 Mbit/s is presented. The chip implements a 16-state EPR4 parity check time variant Viterbi detector and a digital servo. A 24/26 code with parity check improves the robustness to white noise, media noise and to off-track conditions. The device is integrated in a mature 0.35 μm BiCMOS technology with a die size of 13 mm2 (step and repeat) and dissipates 1.9 W (in read mode) at 450 Mbit/s
A 450Mbit/s Parallel Read/Write Channel with Parity Check and 16-State Time Variant Viterbi
CASTELLO, RINALDO
2000-01-01
Abstract
A PRML read/write IC operating up to 450 Mbit/s is presented. The chip implements a 16-state EPR4 parity check time variant Viterbi detector and a digital servo. A 24/26 code with parity check improves the robustness to white noise, media noise and to off-track conditions. The device is integrated in a mature 0.35 μm BiCMOS technology with a die size of 13 mm2 (step and repeat) and dissipates 1.9 W (in read mode) at 450 Mbit/sFile in questo prodotto:
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