A low-power CMOS continuous-time filter is presented. The filter implements a linearization technique which consists of compensating the driver nonlinearity with an opposite load nonlinearity. This results in requiring a lower overdrive to MOS devices and so in power saving. In addition to this the filter features other characteristics which allows one to reduce power consumption. They are: no parasitic poles, no CMFB, no body effect. Finally using digital tuning the performance is optimized for any operation condition. A prototype cell has been designed in a standard 0.5 μm CMOS technology. With a pole frequency in the range 13 MHz-83 MHz (Q=1), the cell features a linear range (1%THD) of 400 mVpp from a 3.3 V supply. The parasitic capacitance is kept lower than 20% of the total capacitance. The power consumption in the tuning range varies from 6 mW to 16 mW
High-frequency CMOS low-power single-branch continuous-time filters
BASCHIROTTO, ANDREA;CASTELLO, RINALDO
2000-01-01
Abstract
A low-power CMOS continuous-time filter is presented. The filter implements a linearization technique which consists of compensating the driver nonlinearity with an opposite load nonlinearity. This results in requiring a lower overdrive to MOS devices and so in power saving. In addition to this the filter features other characteristics which allows one to reduce power consumption. They are: no parasitic poles, no CMFB, no body effect. Finally using digital tuning the performance is optimized for any operation condition. A prototype cell has been designed in a standard 0.5 μm CMOS technology. With a pole frequency in the range 13 MHz-83 MHz (Q=1), the cell features a linear range (1%THD) of 400 mVpp from a 3.3 V supply. The parasitic capacitance is kept lower than 20% of the total capacitance. The power consumption in the tuning range varies from 6 mW to 16 mWI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
