A self-biased CMOS transconductor stage, able to work with a low-voltage supply and low-power dissipation, is proposed. A fully differential configuration in a 0.25 μm minimum lithography technology has been utilized to design the circuit. Paying particular attention to the mismatch problems, a correct sizing of the circuit has been made. With a voltage supply of 1.2 V, the power consumption is 200 μW and the gain bandwidth product is equal to 30 MHz. Utilizing the transconductor proposed here, a biquadratic cell has been simulated: imposing a central frequency of 1 MHz, the filter reaches 1% of THD with 275 mV peak differential sinusoidal input signal, while the total input noise is about 190 μVr.m.s.. With a power consumption of 1 mW, the cell presents a dynamic range of 60 dB and a SNDR peak of 48.6 dB

A self-biased low voltage, low power, CMOS transconductor stage

FEDELI, MICHELE;VACCHI, CARLA
2000-01-01

Abstract

A self-biased CMOS transconductor stage, able to work with a low-voltage supply and low-power dissipation, is proposed. A fully differential configuration in a 0.25 μm minimum lithography technology has been utilized to design the circuit. Paying particular attention to the mismatch problems, a correct sizing of the circuit has been made. With a voltage supply of 1.2 V, the power consumption is 200 μW and the gain bandwidth product is equal to 30 MHz. Utilizing the transconductor proposed here, a biquadratic cell has been simulated: imposing a central frequency of 1 MHz, the filter reaches 1% of THD with 275 mV peak differential sinusoidal input signal, while the total input noise is about 190 μVr.m.s.. With a power consumption of 1 mW, the cell presents a dynamic range of 60 dB and a SNDR peak of 48.6 dB
2000
9780780354821
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11571/7282
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