A Study of Successive Approximation Register ADC Architectures

In the era of all-mobile devices and the Internet of Things, power efficient solutions are required by new applications. Wearables and battery supplied systems are in high demand, asking designers to come up with new ideas for ultra low- power high-performances data converters. Among all the possible architectures, SAR ADCs stand out because of their high efficiency. Besides, the quasi all-digital nature of this topology greatly adapts to the technological scaling and the simple structure better suits to more complex system-level designs. Apart from being an excellent choice as a stand-alone or time-interleaved architecture, SAR ADCs are particularly suited for hybrid solutions that further pushes away the limits of other types of converters, such pipeline or oversampled ADCs. The goal of this thesis is to study the versatility and adaptability of the SAR algorithm for different applications. In order to do so, 3 different projects carried out during the Ph.D. activity are presented. These are 1. An 8-b 700 MS/s Flash-SAR ADC with 86.7 fJ/conversion-step in 65-nm CMOS. 2. A 14-b 33.6 V DR Extended Range ADC for Battery Monitoring. 3. A 200 μW 12-b 8 MS/s SAR ADC for Ultrasound Systems. The presented ADCs highly differ from the performances point of view, but they all share the fact that they use the SAR algorithm to meet the requirements of the given application. The first two projects were fabricated and tested, while the third has been simulated at post-layout level. Project # 1 is a high-speed single-channel ADC for wireline communications. The architecture uses a sub-ranging approach with a flash converter and a multi-bit per cycle SAR ADC. Redundancy is applied to relax the accuracy requirements of the first stages, and a shift-register free logic is implemented. Thresholds in the multi-bit per cycle SAR converter are produced by a special preamplifier that uses an interpolation-like technique. A novel comparator speeds up the overall operation of the converter, by using a built-in preamplifier that initially unbalances the output of the latch. Project # 2 implements an extended-range ADC for monitoring the voltages of a stack of 8 Li-Ion batteries. The system uses an 8-channel TI-incremental ADC for the coarse conversion of the battery cell voltages, and a single SAR ADC for the fine conversion. The high-voltage section is limited to 8 switches and a high- voltage capacitor reducing the cost of the converter. The remaining part of the circuit operates at a nominal 5-V supply. The time-interleaved structure obtains an almost-simultaneous sampling of the battery cells, and the single fine converter limits the mismatch between channels. Project # 3 is a very compact SAR ADC for ultrasound pixel-arrayed systems. The ADC is intended to be used in the acquisition channel of a wearable tran- scranial doppler ultrasound system (TCD) to measure cerebral blood flow velocity (CBFV) at the middle cerebral artery (MCA). There are 64 such channels, so area and power constraints are the most stringent specifications. An hybrid resistive- capacitive structure is used to reduce the area of the DAC, while an asynchronous logic optimises the timing of the converter and the power consumption. Chapter 1 introduces to the reader the most common data converter architec- tures and provides a discussion on the evolution of data converter during the past years. Finally, a research on the state-of-the-art in SAR ADCs is provided. Chap- ters 2, 3 and 4 present the three different projects (# 1, # 2 and # 3), while con- clusions are drawn in Chapter 5. The bibliography is dedicated for each chapter in order to provide a more direct access to the reader.