STMicroelectronics has developed a test chip, Spider-Mem, containing several instances of a 32 KB PCM array macrocell to experimentally characterize the phase change memory cells and investigate its performance when placed in an integrated circuit. This work focuses on the design of analog blocks involved in the programming operation of the phase change memory. A voltage regulator was designed in order to supplies the programming circuitry with an accurate voltage to guarantee the correct operation over the requested power supplies range and temperature interval. The voltage regulator includes a wide digital programmability that allows setting its output voltage to a value between 2.3 V and 5.4 V in order to provide the optimum supply voltage for each type of writing pulse. The operational amplifier of the voltage regulator is the most challenging block, from the performance point of view since it has to drive a current load of up to 20 mA with a small static power consumption and to guarantee a limited output voltage drop when a large current is delivered to the load. To meet these requirements, a three-stage topology stage has been chosen and a cascode compensation network was exploited to reach a faster dynamic response, as well as a larger bandwidth. The experimental characterization of the voltage regulator showed faster recovery and a smaller output voltage drop with respect to a solution designed with a standard compensation technique. In particular, the output-voltage drop has been reduced by 73%, achieving a 180-mV drop, to be compared to a drop of 680 mV in the standard regulator. An analog circuit that reduces the delay in the generation of a large programming current pulse was also implemented on the Spider-Mem chip. The circuit was designed to keep the shape of the current pulses compliant with the specifications and enables the possibility to apply sharp narrow current pulses even in the case of maximum programming parallelism. The experimental characterization of the circuit showed that the proposed solution is able to reach 80% of the required programming current in about 23 ns, thus being almost 5 times faster than the standard current mirror. A charge pump (CP) will be implemented in the future version of the test chip to make the macrocell compatible with a larger variety of applications. In this respect, a charge pump architecture with enhanced efficiency was developed. The proposed CP architecture is based on an enhanced charge transfer technique between differently sized capacitors that allows the charge transfer between adjacent capacitors with a higher efficiency with respect to the case of a standard technique. To demonstrate the effectiveness of the proposed CP architecture, a three-stage structure was designed and compared with three conventional charge pumps. Simulation results showed an improvement in the charge transfer efficiency of the proposed CP by more than 20% when compared to any other of the three conventional charge pumps. Moreover, two theoretical studies were developed to provide useful guidelines to optimize trade-offs commonly encountered in the design of two-stage CMOS operational amplifiers and to be exploited in the design of the next Spider-Mem versions: an enhanced frequency compensation technique and a design strategy aimed to optimize the gain-bandwidth product. The simulation results of an operational amplifier exploiting the enhanced compensation technique showed a 7-time higher gain-bandwidth product utilizing a compensation capacitor about 50 times smaller with respect to the case of a Miller compensation. Finally, the proposed design strategy provides the expressions of the optimum values of transistors sizes, bias currents, and compensation capacitance that allow obtaining the maximum gain-bandwidth product for given specifications in terms of maximum power consumption, total silicon area, and load capacitance.

STMicroelectronics has developed a test chip, Spider-Mem, containing several instances of a 32 KB PCM array macrocell to experimentally characterize the phase change memory cells and investigate its performance when placed in an integrated circuit. This work focuses on the design of analog blocks involved in the programming operation of the phase change memory. A voltage regulator was designed in order to supplies the programming circuitry with an accurate voltage to guarantee the correct operation over the requested power supplies range and temperature interval. The voltage regulator includes a wide digital programmability that allows setting its output voltage to a value between 2.3 V and 5.4 V in order to provide the optimum supply voltage for each type of writing pulse. The operational amplifier of the voltage regulator is the most challenging block, from the performance point of view since it has to drive a current load of up to 20 mA with a small static power consumption and to guarantee a limited output voltage drop when a large current is delivered to the load. To meet these requirements, a three-stage topology stage has been chosen and a cascode compensation network was exploited to reach a faster dynamic response, as well as a larger bandwidth. The experimental characterization of the voltage regulator showed faster recovery and a smaller output voltage drop with respect to a solution designed with a standard compensation technique. In particular, the output-voltage drop has been reduced by 73%, achieving a 180-mV drop, to be compared to a drop of 680 mV in the standard regulator. An analog circuit that reduces the delay in the generation of a large programming current pulse was also implemented on the Spider-Mem chip. The circuit was designed to keep the shape of the current pulses compliant with the specifications and enables the possibility to apply sharp narrow current pulses even in the case of maximum programming parallelism. The experimental characterization of the circuit showed that the proposed solution is able to reach 80% of the required programming current in about 23 ns, thus being almost 5 times faster than the standard current mirror. A charge pump (CP) will be implemented in the future version of the test chip to make the macrocell compatible with a larger variety of applications. In this respect, a charge pump architecture with enhanced efficiency was developed. The proposed CP architecture is based on an enhanced charge transfer technique between differently sized capacitors that allows the charge transfer between adjacent capacitors with a higher efficiency with respect to the case of a standard technique. To demonstrate the effectiveness of the proposed CP architecture, a three-stage structure was designed and compared with three conventional charge pumps. Simulation results showed an improvement in the charge transfer efficiency of the proposed CP by more than 20% when compared to any other of the three conventional charge pumps. Moreover, two theoretical studies were developed to provide useful guidelines to optimize trade-offs commonly encountered in the design of two-stage CMOS operational amplifiers and to be exploited in the design of the next Spider-Mem versions: an enhanced frequency compensation technique and a design strategy aimed to optimize the gain-bandwidth product. The simulation results of an operational amplifier exploiting the enhanced compensation technique showed a 7-time higher gain-bandwidth product utilizing a compensation capacitor about 50 times smaller with respect to the case of a Miller compensation. Finally, the proposed design strategy provides the expressions of the optimum values of transistors sizes, bias currents, and compensation capacitance that allow obtaining the maximum gain-bandwidth product for given specifications in terms of maximum power consumption, total silicon area, and load capacitance.

Analog Circuits Design for Non-Volatile Memories

ZURLA, RICCARDO
2018-03-02

Abstract

STMicroelectronics has developed a test chip, Spider-Mem, containing several instances of a 32 KB PCM array macrocell to experimentally characterize the phase change memory cells and investigate its performance when placed in an integrated circuit. This work focuses on the design of analog blocks involved in the programming operation of the phase change memory. A voltage regulator was designed in order to supplies the programming circuitry with an accurate voltage to guarantee the correct operation over the requested power supplies range and temperature interval. The voltage regulator includes a wide digital programmability that allows setting its output voltage to a value between 2.3 V and 5.4 V in order to provide the optimum supply voltage for each type of writing pulse. The operational amplifier of the voltage regulator is the most challenging block, from the performance point of view since it has to drive a current load of up to 20 mA with a small static power consumption and to guarantee a limited output voltage drop when a large current is delivered to the load. To meet these requirements, a three-stage topology stage has been chosen and a cascode compensation network was exploited to reach a faster dynamic response, as well as a larger bandwidth. The experimental characterization of the voltage regulator showed faster recovery and a smaller output voltage drop with respect to a solution designed with a standard compensation technique. In particular, the output-voltage drop has been reduced by 73%, achieving a 180-mV drop, to be compared to a drop of 680 mV in the standard regulator. An analog circuit that reduces the delay in the generation of a large programming current pulse was also implemented on the Spider-Mem chip. The circuit was designed to keep the shape of the current pulses compliant with the specifications and enables the possibility to apply sharp narrow current pulses even in the case of maximum programming parallelism. The experimental characterization of the circuit showed that the proposed solution is able to reach 80% of the required programming current in about 23 ns, thus being almost 5 times faster than the standard current mirror. A charge pump (CP) will be implemented in the future version of the test chip to make the macrocell compatible with a larger variety of applications. In this respect, a charge pump architecture with enhanced efficiency was developed. The proposed CP architecture is based on an enhanced charge transfer technique between differently sized capacitors that allows the charge transfer between adjacent capacitors with a higher efficiency with respect to the case of a standard technique. To demonstrate the effectiveness of the proposed CP architecture, a three-stage structure was designed and compared with three conventional charge pumps. Simulation results showed an improvement in the charge transfer efficiency of the proposed CP by more than 20% when compared to any other of the three conventional charge pumps. Moreover, two theoretical studies were developed to provide useful guidelines to optimize trade-offs commonly encountered in the design of two-stage CMOS operational amplifiers and to be exploited in the design of the next Spider-Mem versions: an enhanced frequency compensation technique and a design strategy aimed to optimize the gain-bandwidth product. The simulation results of an operational amplifier exploiting the enhanced compensation technique showed a 7-time higher gain-bandwidth product utilizing a compensation capacitor about 50 times smaller with respect to the case of a Miller compensation. Finally, the proposed design strategy provides the expressions of the optimum values of transistors sizes, bias currents, and compensation capacitance that allow obtaining the maximum gain-bandwidth product for given specifications in terms of maximum power consumption, total silicon area, and load capacitance.
STMicroelectronics has developed a test chip, Spider-Mem, containing several instances of a 32 KB PCM array macrocell to experimentally characterize the phase change memory cells and investigate its performance when placed in an integrated circuit. This work focuses on the design of analog blocks involved in the programming operation of the phase change memory. A voltage regulator was designed in order to supplies the programming circuitry with an accurate voltage to guarantee the correct operation over the requested power supplies range and temperature interval. The voltage regulator includes a wide digital programmability that allows setting its output voltage to a value between 2.3 V and 5.4 V in order to provide the optimum supply voltage for each type of writing pulse. The operational amplifier of the voltage regulator is the most challenging block, from the performance point of view since it has to drive a current load of up to 20 mA with a small static power consumption and to guarantee a limited output voltage drop when a large current is delivered to the load. To meet these requirements, a three-stage topology stage has been chosen and a cascode compensation network was exploited to reach a faster dynamic response, as well as a larger bandwidth. The experimental characterization of the voltage regulator showed faster recovery and a smaller output voltage drop with respect to a solution designed with a standard compensation technique. In particular, the output-voltage drop has been reduced by 73%, achieving a 180-mV drop, to be compared to a drop of 680 mV in the standard regulator. An analog circuit that reduces the delay in the generation of a large programming current pulse was also implemented on the Spider-Mem chip. The circuit was designed to keep the shape of the current pulses compliant with the specifications and enables the possibility to apply sharp narrow current pulses even in the case of maximum programming parallelism. The experimental characterization of the circuit showed that the proposed solution is able to reach 80% of the required programming current in about 23 ns, thus being almost 5 times faster than the standard current mirror. A charge pump (CP) will be implemented in the future version of the test chip to make the macrocell compatible with a larger variety of applications. In this respect, a charge pump architecture with enhanced efficiency was developed. The proposed CP architecture is based on an enhanced charge transfer technique between differently sized capacitors that allows the charge transfer between adjacent capacitors with a higher efficiency with respect to the case of a standard technique. To demonstrate the effectiveness of the proposed CP architecture, a three-stage structure was designed and compared with three conventional charge pumps. Simulation results showed an improvement in the charge transfer efficiency of the proposed CP by more than 20% when compared to any other of the three conventional charge pumps. Moreover, two theoretical studies were developed to provide useful guidelines to optimize trade-offs commonly encountered in the design of two-stage CMOS operational amplifiers and to be exploited in the design of the next Spider-Mem versions: an enhanced frequency compensation technique and a design strategy aimed to optimize the gain-bandwidth product. The simulation results of an operational amplifier exploiting the enhanced compensation technique showed a 7-time higher gain-bandwidth product utilizing a compensation capacitor about 50 times smaller with respect to the case of a Miller compensation. Finally, the proposed design strategy provides the expressions of the optimum values of transistors sizes, bias currents, and compensation capacitance that allow obtaining the maximum gain-bandwidth product for given specifications in terms of maximum power consumption, total silicon area, and load capacitance.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11571/1214898
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