High Speed 3D-Integrated Silicon Photonic Optical Receivers in PIC25G and BiCMOS-55nm Technology

This thesis presents 2 versions of 3D-integrated Opto-Electrical Receiver (RX) front-end: RX-I and the RX-II. The Electronic Integrated Circuit (EIC) in both RX is fabricated in a BiCMOS-55nm technology, flipped and placed on top of the Photonic Integrated Circuits (PIC) die through copper pillars. In RX-I chain, a Fully Differential Shunt-Feedback Trans-Impedance Amplifier (FD-SF TIA) is followed by a Limiting Amplifiers (LA) with embedded equalization, output driver and an automatic offset cancellation loop. The whole receiver provides a Trans-Impedance (TI) gain of 76dBΩ with 30GHz bandwidth. By exploiting the FD-SF TIA with low parasitic capacitance of the Germanium dual heterojunction Photo Diode (Ge-PD) in the photonic die, the receiver achieves sensitivity of -15.2dBm OMA at Ge-PD and -10dBm OMA at the Single Mode Fiber (SMF) optical output with Bit Error Rate of 10-12 and PRBS 15. The sensitivity is aligned with state-of-the-art receivers employing discrete photonics and, to authors best knowledge, it is the lowest reported among published 25Gbps receivers exploiting silicon photonics. RX-II is an optical receiver operating up to 50Gbps and reaches OMA sensitivity of 7.5dBm at Germanium dual heterojunction Photo Diode (Ge-PD) with BER of 10-12, PRBS 7 and energy efficiency of 1.8pj/bit. The Analog Front-End (AFE) in the receiver benefits from a modified form of active feedback structure, proposed in the Limiting Amplifier (LA) to maintain high bandwidth also at large input signal, key to avoid Inter Symbol Interference (ISI) and Data Dependent Jitter (DDJ). Moreover, the Fully-Differential Shunt Feedback Trans-Impedance Amplifier (FD-SF TIA) proposed in RX-I at half the data-rate has also been exploited to reduce the input referred noise and improve the sensitivity.