An Extended-Range Hybrid Analog-to-Digital Converter for Audio Applications

The audio subsystem plays undoubtedly a key role in the automotive infotainment system. With the addition of more features and subsystems, there is an increasing demand for providing high performance, less-power hungry and cost-effective solutions for audio systems. The most important component in audio systems are the audio amplifiers, whose main function is the faithful reproduction of the input audio signals at the output with desired power levels and volume, but with very low distortion suppressing the in-band noise. Class-D audio amplifiers can achieve efficiencies of 90-95%, so they are emerging as possible choice and are now being increasingly used in audio systems. Since the real audio signal is in analog format, it requires an interface to convert the audio signal into a high resolution digital audio input for class-D amplifier. The performance of a digital class-D audio amplifier can be enhanced, with improved flexibility and made user-friendly, if analog input-support is added eliminating the need of high resolution digital audio input. This PhD research is aimed to provide analog input support by incorporating a front-end ADC to a digital input class-D audio amplifier without varying the already built amplifier chain. An extended-range hybrid ADC architecture has been designed that exploits the advantages of both incremental ADC and oversampling by combining incremental and Δ⅀ ADC sequentially, and targeting a dynamic range of ≥100 dB for -60 dBFs. The proposed solution includes the conversion of the input signal in two steps, where the coarse conversion is done by a first-order Incremental ADC with 4-bit quantizer to generate the MSBs, whose residual error is further processed and noise shaped by a third-order Δ⅀ ADC with a 5-bit quantizer to generate the LSBs, termed as fine conversion. The front-end first-order incremental ADC employs an additional parallel Flash ADC that directly translates the input signal into a thermometric code and is combined in the feedback with the residual output. This technique relaxes the output swing and slew rate requirements of the incremental opamp and also enhances the input dynamic range. To compensate for the capacitance mismatch in the feedback DAC, a simpler and low-power one-shift DEM technique has been introduced in the parallel path with performance close to the standard DWA compensation technique. The Δ⅀ ADC that processes the residual error of Incremental ADC, uses a cascade of integrators with distributed feedback (CIFB) topology with capacitive input feed-forward architecture (CIFF-CIFB). Because of the small residue generated by the incremental integrator, the circuit uses only half of the comparators in Flash ADC saving area and power costs. The Hybrid ADC generates two 4-bit binary outputs from Incremental converter and 5-bit binary output from the Δ⅀ modulator. After the conversion, post-processing is done off-chip where the output of the incremental ADC is accumulated, delayed and combined with Δ⅀ ADC output with proper synchronization to generate the final output.