D-Band Amplifiers in SiGe BiCMOS for Wireless Backhaul in 5G and Beyond

The never ending demand for wider bandwidth, coupled with the evolution of technology, drives the progress of silicon ICs beyond 100GHz. The wide available spectrum in D-band, 60GHz centered at 140GHz, is being considered for enhanced resolution radars and wireless transceivers with a fiber-like transport capacity, key for network deployment in 5G and beyond. Amplifiers are the key building blocks in wireless transceivers, i.e., in receivers low noise amplifiers restore adequate amplitude before frequency conversion and in transmitters power amplifiers drive the antenna with sufficient power in a most efficient way. Considering the operation of transistors close to fmax of the technology, in D-band, design of amplifiers with sufficient performance is particularly challenging. The Ph.D. activity has been done by following three paths to address different issues: (1) Strategies for compact designs, key for phased array systems where fitting the ICs in dedicated radiating antenna element footprint is challenging. (2) Design approach for gain-bandwidth-product enhancement, important to ensure the full D-band operation. (3) Techniques for efficiency enhancement for power amplifiers in D-band, essential for the most power hungry block. To this regard, this thesis presents 9 D-band amplifiers, i.e., 7 signal amplifiers and 2 power amplifiers. First 4 compact D-band amplifiers use lumped elements in matching networks. In the first two single ended designs, to correctly account for the effects of a non-ideal ground plane, i.e., reactances in current return paths, and coupling of inductors with nearby layout structures, a shielded 2- port, 4-terminal simulation strategy for inductors is proposed and validated by measurements. The approach allows very accurate design of compact amplifiers in D-band. The 1-stage design proves 11.8dB gain at 152GHz and 17.9GHz bandwidth in 0.031mm2. With the 2-stage amplifier, featuring 20.1dB gain at 150GHz with 24.5GHz bandwidth in 0.058mm2, from 2× to 5.7× area reduction is demonstrated against similar SiGe amplifiers in the same frequency band. In the next two designs, the differential topology is developed for robustness against parasitic effects of the non-ideal ground, a key issue with lumped components at high frequency. The 1-stage amplifier reaches 8dB gain at 156GHz and 17.8GHz bandwidth in 0.026mm2 silicon area. The 2-stage amplifier displays 17.4dB gain at 157GHz with 42.7GHz bandwidth in 0.048mm2. Compared to previously reported SiGe amplifiers in similar frequency range, more than 2× core area reduction is demonstrated at comparable gain-bandwidth product. The last three designs uses transmission lines in matching networks. For designed amplifiers, simple, closed-form equations for gain and bandwidth as a function of the load reflection coefficient are derived. Leveraging the results of the analysis, which can be also applied to the lumped-element approach, a single-stage and multi stage stagger-tuned amplifiers are implemented in a SiGe BiCMOS technology. Twoand three-stage amplifiers demonstrate more than 60GHz bandwidth with 20dB and 28dB gain respectively, corresponding to 700GHz and 1.7THz gain-bandwidth product. Normalizing gain and bandwidth to the number of stages and technology fmax, the resulting Figure of Merit is remarkably higher than previously reported silicon amplifiers in the same band. The power amplifiers (PAs) are designed in a single-ended and differential fashion. The PAs exploit the remarkable features of common-base stages to enhance power-added-efficiency in the linear PA operating region. A single-ended PA proves P1dB=16.8dBm with PSAT=17.6dBm at 135GHz. The PAE at P1dB and at P1dB−6dB are 17.1% and 8.5% respectively. With a differential PA the linear output power is increased to P1dB=18.5dBm with PSAT=19.3dBm at 135GHz. The PAE at P1dB and at P1dB−6dB are 12.6% and 6.7% respectively, an improvement of at least 3× against state of the art.