The ever-growing mobile data traffic drives continuous innovations in wireless communications, and the development of new generation mobile network is expected to provide ultra-high data rates. However, the use of spectrally efficient high-order modulations sets stringent phase-noise requirements to frequency synthesizers in the network infrastructure. In this framework, this thesis addresses the challenge of achieving a remarkable advance in the state-of-the-art phase-noise performance of silicon oscillators. First it recognized that given the supply voltage, the phase noise in LC oscillators is reduced by scaling down the inductance and increasing power consumption. However, the Q degradation with too small inductors sets a lower bound on phase noise. To overcome this limit, oscillators evolved from a single core to multi-core, with N oscillators coupled to scale down phase noise ideally by 10 log(N). In this dissertation, two different coupling techniques are compared: active-coupling (i.e., by means of transconductors) and resistive-coupling (i.e., by means of resistors), that is the two most promising topologies to implement a reconfigurable solution by turning on/off oscillators and the coupling stages to scale noise and power consumption. A theoretical analysis of dual-core oscillators examines the mechanism of phase-noise scaling with specific focus on the degradation caused by resonant frequency mismatches between the LC-tanks, proving that resistive-coupling is the more robust coupling technique. The extension to N oscillators, with N >2, is then considered, demonstrating the existing tradeoff between increasing the number N of coupled oscillators and the locking capability, together with the phase noise penalty in presence of resonant frequency mismatches. Closed-form formulas of the locking range and the statistical phase noise degradation, provide deep understanding of the coupling requirements and useful insights on coupled oscillators design. Test-chips of a 20 GHz 16-core class-C VCO is fabricated in 55nm SiGe BiCMOS technology. Measurements demonstrate a record phase noise as low as -130 dBc/Hz at 1MHz offset, at least 8dB lower than state-of -the-art. Power consumption is 840mW, corresponding to 186.6 dBc/Hz Figure of Merit (FoM), while the tuning range is 17.4%. A reconfigurable version of the multi-core oscillator is realized exploiting DC-biased diode-connected bipolar transistors as switches to couple oscillators. Measurements at 1MHz offset from the 19.2GHz carrier show -120dBc/Hz phase noise in dual-core configuration which can be lowered down to -128.8dBc/Hz turning on two-by-two up to 16 resonators. Meanwhile, the power dissipated from the 2.4V supply ranges between 105mW to 948mW. A different approach is finally introduced in this thesis: a technique which breaks the phase noise barrier of conventional LC oscillators. By exploiting the series resonance of a tank, an unprecedent phase noise reduction in a single-core oscillator is experimentally demonstrated. Realized in a 55nm-BiCMOS technology, the series-resonance VCO proves -138dBc/Hz phase noise at 1MHz offset from 10GHz, with 600mW power consumption from 1.2V supply, corresponding to a state-of-the-art 190dBc/Hz FoM. This phase noise is at least 10dB lower than what reported in silicon so far.

Ultra-Low Phase Noise VCOs in SiGe BiCMOS for high-capacity and spectrally-efficient mmWave communications

RICCARDI, DOMENICO
2022-05-06T00:00:00+02:00

Abstract

The ever-growing mobile data traffic drives continuous innovations in wireless communications, and the development of new generation mobile network is expected to provide ultra-high data rates. However, the use of spectrally efficient high-order modulations sets stringent phase-noise requirements to frequency synthesizers in the network infrastructure. In this framework, this thesis addresses the challenge of achieving a remarkable advance in the state-of-the-art phase-noise performance of silicon oscillators. First it recognized that given the supply voltage, the phase noise in LC oscillators is reduced by scaling down the inductance and increasing power consumption. However, the Q degradation with too small inductors sets a lower bound on phase noise. To overcome this limit, oscillators evolved from a single core to multi-core, with N oscillators coupled to scale down phase noise ideally by 10 log(N). In this dissertation, two different coupling techniques are compared: active-coupling (i.e., by means of transconductors) and resistive-coupling (i.e., by means of resistors), that is the two most promising topologies to implement a reconfigurable solution by turning on/off oscillators and the coupling stages to scale noise and power consumption. A theoretical analysis of dual-core oscillators examines the mechanism of phase-noise scaling with specific focus on the degradation caused by resonant frequency mismatches between the LC-tanks, proving that resistive-coupling is the more robust coupling technique. The extension to N oscillators, with N >2, is then considered, demonstrating the existing tradeoff between increasing the number N of coupled oscillators and the locking capability, together with the phase noise penalty in presence of resonant frequency mismatches. Closed-form formulas of the locking range and the statistical phase noise degradation, provide deep understanding of the coupling requirements and useful insights on coupled oscillators design. Test-chips of a 20 GHz 16-core class-C VCO is fabricated in 55nm SiGe BiCMOS technology. Measurements demonstrate a record phase noise as low as -130 dBc/Hz at 1MHz offset, at least 8dB lower than state-of -the-art. Power consumption is 840mW, corresponding to 186.6 dBc/Hz Figure of Merit (FoM), while the tuning range is 17.4%. A reconfigurable version of the multi-core oscillator is realized exploiting DC-biased diode-connected bipolar transistors as switches to couple oscillators. Measurements at 1MHz offset from the 19.2GHz carrier show -120dBc/Hz phase noise in dual-core configuration which can be lowered down to -128.8dBc/Hz turning on two-by-two up to 16 resonators. Meanwhile, the power dissipated from the 2.4V supply ranges between 105mW to 948mW. A different approach is finally introduced in this thesis: a technique which breaks the phase noise barrier of conventional LC oscillators. By exploiting the series resonance of a tank, an unprecedent phase noise reduction in a single-core oscillator is experimentally demonstrated. Realized in a 55nm-BiCMOS technology, the series-resonance VCO proves -138dBc/Hz phase noise at 1MHz offset from 10GHz, with 600mW power consumption from 1.2V supply, corresponding to a state-of-the-art 190dBc/Hz FoM. This phase noise is at least 10dB lower than what reported in silicon so far.
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Descrizione: PhD Thesis Domenico Riccardi
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11571/1454406
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