Design of an ECL-Based Digital-to-Time Converter for Fractional-N Sub-Sampling PLLs in BiCMOS Technology

Applications such as measurement instruments, scientific instrumentation, radiation-hardened systems, and space electronics demand ultra-low close-in phase noise—often down to 100-Hz offset. In an ultra-low phase noise frequency synthesizer, the reference source remains the dominant close-in noise contributor. Sub-sampling phase-locked loops (SSPLLs) inherently offer low in-band phase noise, making them well suited for such applications. However, fractional-N operation—essential for fine frequency resolution—necessitates a digital-to-time converter (DTC), whose nonlinearity and phase noise directly determine the loop’s in-band noise and spur performance. Although extensive research has been devoted to CMOS-based DTCs, these implementations remain limited by flicker noise and are impractical for low-volume, high-reliability systems. In contrast, BiCMOS technology offers low 1/f noise, high transconductance, and radiation tolerance, making it ideal for ultra-low-jitter and low-phase-noise synthesizers. This dissertation presents the analysis, design, and implementation of an Emitter-Coupled Logic (ECL)-based DTC for fractional-N sub-sampling PLLs, realized in GlobalFoundries 130-nm SiGe BiCMOS technology. A comprehensive analytical model is developed to capture delay and integral nonlinearity (INL) behavior, accounting for parasitic and finite-transition effects. The proposed DTC includes a two-stage clock buffer, a differential pair loaded with a custom MOM switched-capacitor array and series load-resistor switching, and a recovery stage. Post-layout simulations demonstrate a systematic INL below 14 fs (0.015 LSB, with LSB = 940 fs) and a standalone phase noise of −157 dBc/Hz at 1-kHz offset for a 100-MHz input. Since a conventional CMOS sub-sampling phase detector (SSPD) cannot directly accept ECL levels without noisy logic conversion, a hybrid bipolar–CMOS SSPD was developed. It directly interfaces with the ECL-based DTC while maintaining low flicker noise and achieves a simulated input-referred phase noise of −173 dBc/Hz at 10-kHz offset for a 10.3-GHz output. To validate the design, a 7-bit ECL-based DTC and the proposed SSPD were fabricated in GF 130-nm BiCMOS technology. Although static measurements show a DTC INL of 115 fs (LSB = 799 fs) at 100 MHz, dynamic evaluation within a fractional-N SSPLL reveals second-order effects not captured by static testing. Using the proposed DTC and SSPD, the SSPLL achieves 100.7-fs jitter over 100 Hz–100 MHz, −110.8 dBc/Hz phase noise at 1-kHz offset, and a −62 dBc spur for a 10-kHz fractional offset at 10.3 GHz. In integer-N mode, the SSPLL exhibits 90.1-fs jitter and −111 dBc/Hz phase noise at 1-kHz offset at 10.3-GHz output frequency. Compared with prior CMOS-based DTC implementations, the proposed approach benefits from the inherently low 1/f noise, and constant-current operation, enabling improved linearity and phase-noise performance without relying on complex digital calibration schemes. These results demonstrate that the proposed architecture is well suited for low-jitter fractional-N SSPLLs targeting scientific, measurement, and space-grade applications.