An Industrial Tool--Driven Framework for Automated Architecture, Schematic, and Layout Design of Analog Integrated Circuits

This dissertation presents an industrial tool-driven methodology for multi-level automation of analog integrated circuit (IC) design, spanning architecture exploration, schematic synthesis, optimization, and layout generation. While digital design flows are highly automated, analog IC design remains largely manual due to complex trade-offs, sensitivity to device matching, and strong dependence on layout quality. At the architecture level, the proposed approach enables automated optimization of power-management circuits using Python-based algorithms integrated with industrial circuit simulators. A DC--DC buck converter is used as a benchmark to demonstrate efficient parameter sizing through constrained sweeps, achieving a peak efficiency of approximately 86\% at 1\,A load under realistic operating conditions while significantly reducing manual effort. At the schematic level, parameterized and technology-independent generators are developed for automatic synthesis of analog and mixed-signal circuits. A resistor network connected to a comparator serves as a benchmark to demonstrate variation-aware optimization that minimizes layout area while maintaining voltage accuracy and robustness. Validation across more than 200\,000 Monte~Carlo samples achieves a 100\% pass rate across all process corners, with a voltage error below 1\%. The automatically generated schematic has been successfully implemented in a silicon prototype, confirming the practical deployability of the proposed methodology. The methodology is further extended to hierarchical generation of SAR ADC sub-blocks, with key contributions including a three-stage evolution from single-ended to differential implementations, automated technology migration, and a dynamic symbol modification framework. At the layout level, the approach incorporates constraint-driven placement and template-based routing to preserve analog symmetry. Comparative results show that template-based routing significantly improves matching and performance compared to unconstrained routing, with automated layout generation completed in under 5\,minutes compared to 3--34\,hours of manual development effort. The framework also supports technology porting through rule-based layer mapping, enabling the reuse of layout templates across different process nodes. All stages are validated using industrial EDA tools, demonstrating scalability, design consistency, and significant reductions in design time. This work shows that systematic automation of analog IC design is achievable without compromising performance or layout quality.