Design and Silicon Validation of a 433.92 MHz ISM Band TR-PPM Transmitter ASIC with Digital Baseband in 65-nm CMOS

Ultra-low power wireless communication is a key requirement for Internet of Things, structural health monitoring, and battery powered sensing systems, where long operating lifetime must be achieved under strict energy and regulatory constraints. In such applications, the radio transmitter often dominates the energy budget, especially when short data packets are transmitted at low duty cycle. This thesis addresses this challenge through the design, implementation, and validation of a 433.92 MHz transmitted reference pulse position modulation (TR-PPM) transmitter ASIC architecture in TSMC-65 nm CMOS technology. The proposed architecture combines narrowband ISM band operation, TR-PPM signaling, and coordinated duty cycling of the RF front-end to decouple high instantaneous RF output power from low average energy consumption. The work follows a measurement driven incremental methodology based on three test chips with increasing integration complexity. TestChip-1 (TC1) validates the RF front-end under pulsed operation, including a 13.56 MHz Pierce crystal oscillator, an integer N-PLL with a divide by 32 feedback divider and ring VCO, and a Class-E power amplifier. Silicon measurements demonstrate frequency synthesis at 433.92 MHz, PLL settling within approximately 3 µs, crystal oscillation startup after 2.64 µs, and frequency settling to 13.55 MHz within 60 µs. The measured RF output power reaches 14.88 dBm, while pulsed measurements confirm stable RF burst generation and fast enable controlled operation. Building on TC1, TestChip-2 (TC2) introduces fixed frame digital control and mixed signal interfaces, while TestChip-3 (TC3) integrates the enhanced RF front end with the complete programmable digital baseband and system level control logic. A configurable digital baseband architecture is developed to support autonomous TR-PPM frame generation. The digital subsystem includes SPI based configuration, register memory, CRC-16 generation, payload serialization, TR-PPM symbol scheduling, and deterministic enable sequencing of the RF blocks. This architecture enables programmable frame construction and precise pulse timing without requiring embedded firmware execution inside the ASIC. The digital baseband, together with the integrated TC2 and TC3 architectures, is validated through functional and post-layout simulations, while full silicon characterization of the later integrated test chips remains part of the next experimental phase. The measurement results confirm the feasibility of aggressively duty cycling a PLL based narrowband transmitter for pulse-based communication. Measurement based energy analysis indicates energy consumption on the order of 100 to 120 nJ per bit, depending on the duty cycling configuration. The main novelty of this work lies in combining TR-PPM modulation, PLL based sub-GHz carrier generation, coordinated RF block activation, and a programmable digital baseband within a scalable mixed-signal CMOS transmitter architecture. The proposed design provides a practical foundation for future low power wireless sensor nodes and fully integrated TR-PPM communication systems.