Design and Implementation of a 28 nm CMOS Bulk RISC-V Single-Core Microprocessor and Peripheral Subsystems

This thesis reports the comprehensive design, physical implementation, and experimental characterization of a RISC-V microprocessor integrated in 28nm Bulk CMOS technology, specifically optimized for aerospace applications. The research was conducted within the MUSA (Multilayered Urban Sustainability Action) project, funded by the PNRR, in collaboration with Thales Alenia Space Italy (TASI). The primary objective is the development of radiation-hardened Application-Specific Integrated Circuits (ASICs) to replace legacy components and FPGA-based reconfigurable logic in space missions. A key contribution of this work is the technological selection of the 28nm Bulk CMOS process over FD-SOI. While FD-SOI offers power advantages, its thick Buried Oxide (BOX) layer is highly susceptible to charge trapping, leading to severe back-channel effects in high-dose environments. In contrast, the Bulk process provides superior intrinsic resistance to Total Ionizing Dose (TID), a critical requirement for long-term missions (e.g., LISA, JUICE, Parker Solar Probe) where cumulative exposure can exceed 10 MRad. The inherent leakage current of the Bulk process was mitigated through dedicated power management and physical optimization at the design stage. The core architecture is based on the open-source RV32I (RISC-V Base Integer 32-bit) Instruction Set Architecture (ISA). This modular approach allows for high hardware customizability and the integration of dedicated accelerators for AI/ML, enabling a single-chip solution to replace multiple discrete components, thus streamlining the rigorous aerospace qualification flow. The implementation phase involved both RTL design and physical synthesis, targeting a single-cycle core operating at 100 MHz. The final ASIC occupies an area of 0.0625 mm² (52.36 kGE), integrating 33,288 standard cells and approximately 209,449 MOS transistors. Verification was performed through a standardized testbench strategy using Cadence EDA tools for post-layout simulations, followed by experimental validation on a custom PCB. Power characterization was conducted using a custom firmware benchmark designed to maximize switching activity. Experimental laboratory measurements yielded a static power of 45 µW and a dynamic power of 1.62 mW, showing close correlation with post-layout simulations (9 µW and 1.479 mW, respectively) and demonstrating competitive performance relative to the state-of-the-art. Additionally, the thesis explores the design of essential Rad-Hard-by-Design (RHBD) IP blocks necessary for aerospace System-on-Chip (SoC) integration, including RHBD SRAMs, Phase-Locked Loops (PLLs), cache controllers for external memory interfacing, and a Floating Point Unit (FPU) to enhance computational throughput. The work concludes with a summary of the achieved milestones and an outlook on future architectural developments.