Integrated Driving Architecture for Energy- and Area-Efficient Synchronous Buck Converters in BCD Technology for Automotive Applications

This dissertation examines the design and experimental validation of a fully integrated driving architecture for high-efficiency synchronous DC–DC buck converters, motivated by power management needs in automotive infotainment, ADAS, and body electronics. Such systems require converter solutions that are efficient, compact, and tolerant to frequent load variations, conditions that tend to expose trade-offs between switching efficiency, parasitic effects, and silicon area. In response, the work focuses on a monolithic integrated synchronous half-bridge gate-drive architecture and its power stage, targeting a balanced combination of energy efficiency, compact silicon implementation, on-chip functional integration, and robust high-frequency operation. The proposed system is implemented in STMicroelectronics BCD110AP junction-isolated technology, enabling monolithic integration of power devices, analog interfaces, and control logic. The gate driver is co-designed with the power stage for high-frequency operation and incorporates Adaptive Dead-Time Control (ADTC), a compact Open-loop Gate-Drive Boost (GB), a Capacitive Floating Level Shifter (CF-LS), and an integrated NMOS bootstrap switch. The CF-LS enables energy-efficient high-side signal transfer with zero static power while maintaining robust operation under high CMTI. The ADTC minimizes rising and falling dead times across varying loads, reducing body-diode conduction and reverse-recovery losses, whereas the GB accelerates high-side switching to reduce switching-overlap losses without increasing peak switching-node slew rate. The active bootstrap switch lowers charging losses, resulting in improved switching performance, reduced parasitics, and a compact integrated converter solution. The work is validated through two silicon tape-outs. The standalone CF-LS achieves 1.525 ns propagation delay and 29.77pJ transition energy at 40V, independent of VIN, with 20 V/ns slew-rate immunity, 30% mismatch tolerance, a FoM_{lvlshft} of 2.68 ns·pJ/μm³·V (≈2× improvement over recent designs), and operation up to 55MHz. The integrated gate driver with a synchronous NMOS–NMOS power stage reduces rising and falling dead times to <1 ns and 0–2ns, respectively, while the open-loop GB shortens the switching-node rise time by 47% (47ns to 25ns) without degrading peak dV_LX/dt. Operating from 3–36V, it supports switching frequencies up to 3MHz, delivers 4.4A output current with only 2.43μA quiescent current, and achieves 19.2ns and 15 ns high-side and low-side propagation delays. Experimental measurements demonstrate peak efficiencies of 97.91% for a 10 V/5V conversion ratio and 98.2% for 18 V/12V, while achieving up to 7.51% absolute efficiency improvement and 0.92W converter power-loss reduction through the combined ADTC and GB techniques. The reduced switching losses lower the junction temperature by up to 40.5 ◦C and the package surface temperature by 38.3◦C, substantially improving thermal performance and operating margin. Furthermore, the proposed converter achieves a Power-Efficiency Density Figure-of-Merit (FoM) of 11.09W·MHz/mm2 for a 12 V/5V conversion ratio and 44.36W·MHz/mm2 for 24V/12V, representing approximately a 1.95× improvement over previously reported integrated buck converters. Overall, this dissertation shows that addressing switching-related loss mechanisms through integrated gate-driver innovation enables substantial improvements in converter efficiency, thermal behavior, and power density. The proposed architecture offers a compact, experimentally validated solution for next-generation high-frequency monolithic synchronous buck converters and provides practical design methodologies for future integrated power-management systems.