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EnglishA four-quadrant analog multiplier based on a simple, very linear, and fast BiCMOS transconductor using MOS transistors operating in the triode region and NPN bipolar devices is presented. The four quadrant operation is obtained by crosscoupling-in a Gilbert-cell fashion-two transconductors with a third stage used to modulate the transconductances of the former two. A chip prototype of the multiplier has been integrated in a 1.2-μm BiCMOS process to validate the idea. It has been designed to achieve high linearity on both inputs: measured results show a total harmonic distortion (THD) of less than -40 dB with a 3-V peak-to-peak input signal at 5 MHz from a 5-V supply and an output -3 dB bandwidth of 100 MHz while dissipating 4 mW from a 3-V supply. The integrated chip prototype active area is 1 mm2
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| Titolo: | A 100-MHz 4-mW four-quadrant BiCMOS analog multiplier | |
| Autori: | ||
| Data di pubblicazione: | 1997 | |
| Rivista: | ||
| Abstract: | A four-quadrant analog multiplier based on a simple, very linear, and fast BiCMOS transconductor using MOS transistors operating in the triode region and NPN bipolar devices is presented. The four quadrant operation is obtained by crosscoupling-in a Gilbert-cell fashion-two transconductors with a third stage used to modulate the transconductances of the former two. A chip prototype of the multiplier has been integrated in a 1.2-μm BiCMOS process to validate the idea. It has been designed to achieve high linearity on both inputs: measured results show a total harmonic distortion (THD) of less than -40 dB with a 3-V peak-to-peak input signal at 5 MHz from a 5-V supply and an output -3 dB bandwidth of 100 MHz while dissipating 4 mW from a 3-V supply. The integrated chip prototype active area is 1 mm2 | |
| Handle: | http://hdl.handle.net/11571/104174 | |
| Appare nelle tipologie: | 1.1 Articolo in rivista |
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