This paper presents a continuous-time third-order ΣΔ modulator designed for closing the feedback loop of a digital class-D audio amplifier. The closed-loop digital class-D amplifier fully exploits the potential of the used 40-nm CMOS technology to achieve at the same time the flexibility of digital implementations and the performance of analog solutions. The proposed ΣΔ modulator consumes 1.7 mW from a 1.1-V power supply, achieving 101-dB dynamic-range (DR) and 72-dB peak signal-tonoise and distortion ratio (SNDR). The active-RC implementation allows the 1.1-V ΣΔ modulator inputs to be directly connected to the 5-V class-D amplifier power stage outputs and inherently guarantees third-order anti-aliasing filtering

A 40-nm CMOS, 1.1-V, 101-dB Dynamic-Range, 1.7-mW Continuous-Time ΣΔ ADC for a Digital Closed-Loop Class-D Amplifier

DONIDA, ACHILLE;MALCOVATI, PIERO;
2015-01-01

Abstract

This paper presents a continuous-time third-order ΣΔ modulator designed for closing the feedback loop of a digital class-D audio amplifier. The closed-loop digital class-D amplifier fully exploits the potential of the used 40-nm CMOS technology to achieve at the same time the flexibility of digital implementations and the performance of analog solutions. The proposed ΣΔ modulator consumes 1.7 mW from a 1.1-V power supply, achieving 101-dB dynamic-range (DR) and 72-dB peak signal-tonoise and distortion ratio (SNDR). The active-RC implementation allows the 1.1-V ΣΔ modulator inputs to be directly connected to the 5-V class-D amplifier power stage outputs and inherently guarantees third-order anti-aliasing filtering
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11571/1079785
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