A highly linear receiver (RX) front end with integrated hybrid transformer (HT) for frequency-division duplexing mobile communications is reported. The HT, implemented with a three-winding coplanar transformer, is used to interface the RX front end with the antenna and the power amplifier. The primary is driven at its center tap with the transmitted signal and at one input with the antenna signal, while the other input is connected to an on-chip programmable balancing impedance. The two secondary drives a differential push–pull common-gate low-noise amplifier (LNA). Assuming a perfectly linear hybrid only 45 dB of transmitter (TX)–RX isolation and 35 dB of common-mode rejection are required to meet the intermodulation specs thanks to the +25-dBm receiver IIP3. This would drastically simplify hybrid balancing and adaptation loop. Cascaded noise figure of duplexer, LNA, and baseband is below 6.7 dB and TX insertion loss below 4.3 dB from 1.7 to 2.1 GHz. The implemented prototype in 28-nm CMOS has an active area of 0.7 mm2 and requires only 26 mW.

A +25 dBm IIP3 1.7-2.1 GHz FDD Receiver Front-End with Integrated Hybrid-Transformer in 28nm CMOS

FABIANO, IVAN;RAMELLA, MATTEO;MANSTRETTA, DANILO
;
CASTELLO, RINALDO
2017-01-01

Abstract

A highly linear receiver (RX) front end with integrated hybrid transformer (HT) for frequency-division duplexing mobile communications is reported. The HT, implemented with a three-winding coplanar transformer, is used to interface the RX front end with the antenna and the power amplifier. The primary is driven at its center tap with the transmitted signal and at one input with the antenna signal, while the other input is connected to an on-chip programmable balancing impedance. The two secondary drives a differential push–pull common-gate low-noise amplifier (LNA). Assuming a perfectly linear hybrid only 45 dB of transmitter (TX)–RX isolation and 35 dB of common-mode rejection are required to meet the intermodulation specs thanks to the +25-dBm receiver IIP3. This would drastically simplify hybrid balancing and adaptation loop. Cascaded noise figure of duplexer, LNA, and baseband is below 6.7 dB and TX insertion loss below 4.3 dB from 1.7 to 2.1 GHz. The implemented prototype in 28-nm CMOS has an active area of 0.7 mm2 and requires only 26 mW.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11571/1190429
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