Design and automated characterization of a 10 bit SAR ADC for diffraction imaging at X-ray FELs

This thesis work presents the design and the characterization of a time interleaved Successive Approximation Register (SAR) Analog to Digital Converter (ADC), part of the readout channel for the PixFEL detector. The PixFEL project aims at substantially advancing the state-of-the-art in the field of 2D X-ray imaging for applications at the next generation Free Electron Laser (FEL) facilities, through the adoption of cutting-edge microelectronic technologies and innovative design and architectural solutions. The unprecedented features of X-ray free electron lasers, capable of producing photon pulses with outstanding brightness and ultra-short duration, promise to revolutionize a number of research fields, including structural biology and chemistry, material science and nuclear and molecular physics. The PixFEL project is pursuing the development of a 110 um pitch, four side buttable tile for a large area X-ray imager. For this purpose, the PixFEL collaboration is developing the fundamental building blocks of the front-end readout channel covering the 1 to 10^4 photons input dynamic range, with single photon resolution at small signals, at both 1 keV and 10 keV of energy and with the capability to be operated at the high (1 MHz or larger) rates foreseen for the future X-FEL machines. The fundamental building blocks of the readout chip have been designed in a 65 nm CMOS technology by TSMC and consist of a front-end analog channel and a time interleaved 10 bit successive approximation register (SAR) ADC for in pixel digitization of the signal. A 10 bit converter was chosen to guarantee single photon resolution at small signals, at the cost of some increase in quantization noise at large signals, where it is largely exceeded by Poisson noise. The ADC is based on a charge redistribution architecture, implemented through a split capacitor DAC approach to reduce the circuit area. The discriminator includes a preamplification block, also used to minimize kick-back noise effects, a second gain stage and a latch. For the sampling switch, a bootstrap scheme has been designed, in order to guarantee the maximum switch conductance over the whole input range [0.2; 1] V. The choice of a time-interleaved structure serves the purpose of speeding up the ADC operation, while avoiding large current peaks during the charging phase of the capacitive DAC. Four versions of the ADC layout have been designed for a test chip. Depending on the adopted solution, the area of the converter can vary from (108 x 74) um^2 to (108 x 58) um^2, compatible with the target pitch of the pixel of 110 um. Characterization of the ADC prototypes included in the test chip provided encouraging results. The maximum DNL and INL obtained from the most promising structure are < 1 LSB and 4.08 LSB, respectively. Such a high INL value may degrade the ADC performance and results in increased harmonic distortion when the ADC is used for dynamic signal sampling and reconstruction. In applications like the one considered here, INL effects can be accounted for by suitably calibrating the channel response. All the measurements were taken with the ADC operated at a clock maximum frequency of 20 MHz, resulting in a sampling frequency of about 1.82 MHz. In the same conditions, a mean SNDR (signal-to-noise and distortion ratio) of about 50.39 dB, corresponding to an equivalent number of bits (ENOB) of 8.08, was measured feeding the ADC with a full scale sinusoidal input. Since the SNDR is worsened by the distortion introduced by the integral non linearity, the input noise was evaluated from static measurements as the sigma of an error function fitting the probability that the ADC output exceeds a given code. The mean input noise for the most promising structures turns out to be around 0.4 LSB.