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EnglishTo meet the requirements of future SAW-less frequency-division duplexing (FDD) and phased-array receivers, the linearity of the Low-Noise Transconductance-Amplifier (LNTA) should be considerably improved. In this paper, a highly-linear common-gate (CG) amplifier is presented that can be directly connected to the antenna. The LNTA operates in current-mode and is not power-matched to the antenna. In this way, noise and distortion of the active devices are strongly suppressed. Optimum LNTA driving impedance is provided by a transformer-based LC resonant network, while the LNTA core consists of a complementary cross-coupled CG stage to save power. The impact of passive losses is minimized using the noise-matching technique. Furthermore, the effect of source impedance variation on IIP3, NF and gain is also investigated. The measured IIP3 of the LNTA is more than 25 dBm from 1.5 to 2.8 GHz. The P-1dB gain compression is also +8 dBm. The chip is implemented in 28 nm CMOS and has an active area of 0.29 mm(2) and draws only 8 mA from a 1.8 V supply.
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| Titolo: | A 1.5–2.8 GHz current-mode LNTA achieving >25 dBm IIP3 and +8 dBm P-1dB gain compression | |
| Autori: | ||
| Data di pubblicazione: | 2019 | |
| Rivista: | ||
| Abstract: | To meet the requirements of future SAW-less frequency-division duplexing (FDD) and phased-array receivers, the linearity of the Low-Noise Transconductance-Amplifier (LNTA) should be considerably improved. In this paper, a highly-linear common-gate (CG) amplifier is presented that can be directly connected to the antenna. The LNTA operates in current-mode and is not power-matched to the antenna. In this way, noise and distortion of the active devices are strongly suppressed. Optimum LNTA driving impedance is provided by a transformer-based LC resonant network, while the LNTA core consists of a complementary cross-coupled CG stage to save power. The impact of passive losses is minimized using the noise-matching technique. Furthermore, the effect of source impedance variation on IIP3, NF and gain is also investigated. The measured IIP3 of the LNTA is more than 25 dBm from 1.5 to 2.8 GHz. The P-1dB gain compression is also +8 dBm. The chip is implemented in 28 nm CMOS and has an active area of 0.29 mm(2) and draws only 8 mA from a 1.8 V supply. | |
| Handle: | http://hdl.handle.net/11571/1304366 | |
| Appare nelle tipologie: | 1.1 Articolo in rivista |
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