A Power-Efficient Two-Channel Time-Interleaved SD Modulator for Broadband Applications

A two-channel time-interleaved second-order sigma-delta modulator for broadband applications including asymmetrical digital subscriber line (ADSL) is presented. The proposed two-channel Sigma-Delta modulator uses a single integrator channel which does not require additional active elements for the quantizer input generation, since the integrator outputs are directly used as the input of the quantizers. As a result, the entire modulator can be implemented using only two op-amps, which is beneficial for both power consumption and area. Furthermore, this architecture is robust to channel mismatch effects and can operate with a simple clocking scheme. The Sigma-Delta modulator achieves a dynamic range of 85 dB over a 1.1-MHz signal band- width with an effective clock frequency of 132 MHz. The circuit is implemented in 0.18-um CMOS technology using metal–insulator–metal capacitors. The total power consumption of the Sigma-Delta modulator is 5.4 mW from a 1.8-V supply and occupies an active area of 1.1 mm^2.