A μtrench Phase-Change Memory (PCM) cell with MOSFET selector and its integration in a 4-Mb experimental chip fabricated in 0.18-μm CMOS technology are presented. A cascode bitline biasing scheme allows read and write voltages to be fed to the addressed storage elements with the required accuracy. The high-performance capabilities of PCM cells were experimentally investigated. A read access time of 45 ns was measured together with a write throughput of 5 MB/s, which represents an improved performance as compared to NOR Flash memories. Programmed cell current distributions on the 4-Mb array demonstrate an adequate working window and, together with first endurance measurements, assess the feasibility of PCMs in standard CMOS technology with few additional process modules.

4-Mb MOSFET-selected µtrench phase-change memory experimental chip

BOFFINO, CHIARA;BONIZZONI, EDOARDO;TORELLI, GUIDO;
2005

Abstract

A μtrench Phase-Change Memory (PCM) cell with MOSFET selector and its integration in a 4-Mb experimental chip fabricated in 0.18-μm CMOS technology are presented. A cascode bitline biasing scheme allows read and write voltages to be fed to the addressed storage elements with the required accuracy. The high-performance capabilities of PCM cells were experimentally investigated. A read access time of 45 ns was measured together with a write throughput of 5 MB/s, which represents an improved performance as compared to NOR Flash memories. Programmed cell current distributions on the 4-Mb array demonstrate an adequate working window and, together with first endurance measurements, assess the feasibility of PCMs in standard CMOS technology with few additional process modules.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11571/135890
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