This letter presents 1-stage and 2-stage compact D-band amplifiers with lumped-element matching networks implemented in 55 nm SiGe BiCMOS. To correctly account for the effects of a nonideal ground plane, i.e., reactances in current return paths, and coupling of inductors with nearby layout structures, a shielded 2-port, 4-terminal simulation strategy for inductors is proposed. Validated by measurements, the approach allows very accurate design of compact amplifiers in D-band. The 1-stage design proves 11.8 dB gain at 152 GHz and 17.9 GHz bandwidth in 0.031 mm2. With the 2-stage amplifier, featuring 20.1 dB gain at 150 GHz with 24.5 GHz bandwidth in 0.058 mm2, from 2 imes to 5.7 imes area reduction is demonstrated against similar SiGe amplifiers in the same frequency band.

Design of Compact D-Band Amplifiers with Accurate Modeling of Inductors and Current Return Paths in 55-nm SiGe BiCMOS

Petricli I.;Mazzanti A.
2020

Abstract

This letter presents 1-stage and 2-stage compact D-band amplifiers with lumped-element matching networks implemented in 55 nm SiGe BiCMOS. To correctly account for the effects of a nonideal ground plane, i.e., reactances in current return paths, and coupling of inductors with nearby layout structures, a shielded 2-port, 4-terminal simulation strategy for inductors is proposed. Validated by measurements, the approach allows very accurate design of compact amplifiers in D-band. The 1-stage design proves 11.8 dB gain at 152 GHz and 17.9 GHz bandwidth in 0.031 mm2. With the 2-stage amplifier, featuring 20.1 dB gain at 150 GHz with 24.5 GHz bandwidth in 0.058 mm2, from 2 imes to 5.7 imes area reduction is demonstrated against similar SiGe amplifiers in the same frequency band.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11571/1363855
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