The demand of larger bandwidth and more efficient architectures have pushed many research groups to investigate a new kind of transceiver called Full-Duplex (FD). This topology potentially increases spectral efficiency of a factor of two compared to well-known architectures like Time Division Duplexing (TDD) and Frequency Division Duplexing (FDD). The main challenge comes from the transmitter (TX) leakage which falls in the receiver (RX) path and degrades its signal integrity. The required TX suppression varies from 90 to 120dB. In order to get this target, the FD receiver has three different cancellation processes. The first employs a hybrid transformer which is a four ports network that interfaces the TX, the RX, the antenna and a tuneable impedance called “Balancing”. The balancing goal is to emulate in frequency the antenna impedance. Once this condition is fulfilled, the hybrid transformer behaves like an ideal circulator and the transmitter is electrically disconnected from the receiver. The antenna impedance can change rapidly in frequency, therefore, only 40dB of isolation (ISO) is considered a reachable value. The second cancellation process is realized with a Digital-to-Analog (DAC) converter that works in current mode. Its target is to cancel TX leakage current that comes from the first receiver building block, the Low Noise Transconductance Amplifier (LNTA). To provide a proper current in magnitude and phase, an adaptive digital filter analyses the receiver impulse response and cancels out the current leakage. The adaptive filter, used for the DAC, can suppress only linear contributions which are strictly correlated to TX signal. The third cancellation step wants to remove TX noise/distortion contributions. In this case, a mixer-first auxiliary receiver (AUX-RX) down-converts TX signal and, another, adaptive digital filter combines the two receivers’ output to get an extra cancellation. The auxiliary RX is also suitable to reduce reciprocal mixing due to large TX leakage. The receivers have been implemented in TSMC 28nm technology. The main RX has baseband gain, NF and In-Band IIP3 equal to 33dB, 6,4dB and 15dBm, respectively. Instead, the auxiliary receiver has -7dB, 41dB and 60dBm as before. The AUX-RX has competitive SINAD compares to other works in literature. Simulations show an overall suppression larger than 90dB and main RX NF degradation less than 2dB. In this manuscript two other works are illustrated with measurement results. The former is a mixer-first topology designed in TSMC 40nm to prove that it can realize high SNDR. The latter is another receiver which employs a Single-Ended to Differential LNA. Its application is focused on Multi-Input-Multi-Output (MIMO) and Carrier Aggregation (CA) scenarios where the count pad is critical. In this case, the baseband gain, the NF and the Out-of-Band IIP3 are 48dB, 3,4dB and -3,7 dBm, respectively. This chip has been designed in TSMC 28nm technology and occupied an active area of only 0.08mm2. Its power consumption is 22mW.

The demand of larger bandwidth and more efficient architectures have pushed many research groups to investigate a new kind of transceiver called Full-Duplex (FD). This topology potentially increases spectral efficiency of a factor of two compared to well-known architectures like Time Division Duplexing (TDD) and Frequency Division Duplexing (FDD). The main challenge comes from the transmitter (TX) leakage which falls in the receiver (RX) path and degrades its signal integrity. The required TX suppression varies from 90 to 120dB. In order to get this target, the FD receiver has three different cancellation processes. The first employs a hybrid transformer which is a four ports network that interfaces the TX, the RX, the antenna and a tuneable impedance called “Balancing”. The balancing goal is to emulate in frequency the antenna impedance. Once this condition is fulfilled, the hybrid transformer behaves like an ideal circulator and the transmitter is electrically disconnected from the receiver. The antenna impedance can change rapidly in frequency, therefore, only 40dB of isolation (ISO) is considered a reachable value. The second cancellation process is realized with a Digital-to-Analog (DAC) converter that works in current mode. Its target is to cancel TX leakage current that comes from the first receiver building block, the Low Noise Transconductance Amplifier (LNTA). To provide a proper current in magnitude and phase, an adaptive digital filter analyses the receiver impulse response and cancels out the current leakage. The adaptive filter, used for the DAC, can suppress only linear contributions which are strictly correlated to TX signal. The third cancellation step wants to remove TX noise/distortion contributions. In this case, a mixer-first auxiliary receiver (AUX-RX) down-converts TX signal and, another, adaptive digital filter combines the two receivers’ output to get an extra cancellation. The auxiliary RX is also suitable to reduce reciprocal mixing due to large TX leakage. The receivers have been implemented in TSMC 28nm technology. The main RX has baseband gain, NF and In-Band IIP3 equal to 33dB, 6,4dB and 15dBm, respectively. Instead, the auxiliary receiver has -7dB, 41dB and 60dBm as before. The AUX-RX has competitive SINAD compares to other works in literature. Simulations show an overall suppression larger than 90dB and main RX NF degradation less than 2dB. In this manuscript two other works are illustrated with measurement results. The former is a mixer-first topology designed in TSMC 40nm to prove that it can realize high SNDR. The latter is another receiver which employs a Single-Ended to Differential LNA. Its application is focused on Multi-Input-Multi-Output (MIMO) and Carrier Aggregation (CA) scenarios where the count pad is critical. In this case, the baseband gain, the NF and the Out-of-Band IIP3 are 48dB, 3,4dB and -3,7 dBm, respectively. This chip has been designed in TSMC 28nm technology and occupied an active area of only 0.08mm2. Its power consumption is 22mW.

A Higly-Linear Full-Duplex Receiver With Auxiliary Path and Adaptive Self-Interference Cancellation

PREVEDELLI, DARIO
2021-03-19

Abstract

The demand of larger bandwidth and more efficient architectures have pushed many research groups to investigate a new kind of transceiver called Full-Duplex (FD). This topology potentially increases spectral efficiency of a factor of two compared to well-known architectures like Time Division Duplexing (TDD) and Frequency Division Duplexing (FDD). The main challenge comes from the transmitter (TX) leakage which falls in the receiver (RX) path and degrades its signal integrity. The required TX suppression varies from 90 to 120dB. In order to get this target, the FD receiver has three different cancellation processes. The first employs a hybrid transformer which is a four ports network that interfaces the TX, the RX, the antenna and a tuneable impedance called “Balancing”. The balancing goal is to emulate in frequency the antenna impedance. Once this condition is fulfilled, the hybrid transformer behaves like an ideal circulator and the transmitter is electrically disconnected from the receiver. The antenna impedance can change rapidly in frequency, therefore, only 40dB of isolation (ISO) is considered a reachable value. The second cancellation process is realized with a Digital-to-Analog (DAC) converter that works in current mode. Its target is to cancel TX leakage current that comes from the first receiver building block, the Low Noise Transconductance Amplifier (LNTA). To provide a proper current in magnitude and phase, an adaptive digital filter analyses the receiver impulse response and cancels out the current leakage. The adaptive filter, used for the DAC, can suppress only linear contributions which are strictly correlated to TX signal. The third cancellation step wants to remove TX noise/distortion contributions. In this case, a mixer-first auxiliary receiver (AUX-RX) down-converts TX signal and, another, adaptive digital filter combines the two receivers’ output to get an extra cancellation. The auxiliary RX is also suitable to reduce reciprocal mixing due to large TX leakage. The receivers have been implemented in TSMC 28nm technology. The main RX has baseband gain, NF and In-Band IIP3 equal to 33dB, 6,4dB and 15dBm, respectively. Instead, the auxiliary receiver has -7dB, 41dB and 60dBm as before. The AUX-RX has competitive SINAD compares to other works in literature. Simulations show an overall suppression larger than 90dB and main RX NF degradation less than 2dB. In this manuscript two other works are illustrated with measurement results. The former is a mixer-first topology designed in TSMC 40nm to prove that it can realize high SNDR. The latter is another receiver which employs a Single-Ended to Differential LNA. Its application is focused on Multi-Input-Multi-Output (MIMO) and Carrier Aggregation (CA) scenarios where the count pad is critical. In this case, the baseband gain, the NF and the Out-of-Band IIP3 are 48dB, 3,4dB and -3,7 dBm, respectively. This chip has been designed in TSMC 28nm technology and occupied an active area of only 0.08mm2. Its power consumption is 22mW.
19-mar-2021
The demand of larger bandwidth and more efficient architectures have pushed many research groups to investigate a new kind of transceiver called Full-Duplex (FD). This topology potentially increases spectral efficiency of a factor of two compared to well-known architectures like Time Division Duplexing (TDD) and Frequency Division Duplexing (FDD). The main challenge comes from the transmitter (TX) leakage which falls in the receiver (RX) path and degrades its signal integrity. The required TX suppression varies from 90 to 120dB. In order to get this target, the FD receiver has three different cancellation processes. The first employs a hybrid transformer which is a four ports network that interfaces the TX, the RX, the antenna and a tuneable impedance called “Balancing”. The balancing goal is to emulate in frequency the antenna impedance. Once this condition is fulfilled, the hybrid transformer behaves like an ideal circulator and the transmitter is electrically disconnected from the receiver. The antenna impedance can change rapidly in frequency, therefore, only 40dB of isolation (ISO) is considered a reachable value. The second cancellation process is realized with a Digital-to-Analog (DAC) converter that works in current mode. Its target is to cancel TX leakage current that comes from the first receiver building block, the Low Noise Transconductance Amplifier (LNTA). To provide a proper current in magnitude and phase, an adaptive digital filter analyses the receiver impulse response and cancels out the current leakage. The adaptive filter, used for the DAC, can suppress only linear contributions which are strictly correlated to TX signal. The third cancellation step wants to remove TX noise/distortion contributions. In this case, a mixer-first auxiliary receiver (AUX-RX) down-converts TX signal and, another, adaptive digital filter combines the two receivers’ output to get an extra cancellation. The auxiliary RX is also suitable to reduce reciprocal mixing due to large TX leakage. The receivers have been implemented in TSMC 28nm technology. The main RX has baseband gain, NF and In-Band IIP3 equal to 33dB, 6,4dB and 15dBm, respectively. Instead, the auxiliary receiver has -7dB, 41dB and 60dBm as before. The AUX-RX has competitive SINAD compares to other works in literature. Simulations show an overall suppression larger than 90dB and main RX NF degradation less than 2dB. In this manuscript two other works are illustrated with measurement results. The former is a mixer-first topology designed in TSMC 40nm to prove that it can realize high SNDR. The latter is another receiver which employs a Single-Ended to Differential LNA. Its application is focused on Multi-Input-Multi-Output (MIMO) and Carrier Aggregation (CA) scenarios where the count pad is critical. In this case, the baseband gain, the NF and the Out-of-Band IIP3 are 48dB, 3,4dB and -3,7 dBm, respectively. This chip has been designed in TSMC 28nm technology and occupied an active area of only 0.08mm2. Its power consumption is 22mW.
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Descrizione: Highly–Linear Full-Duplex Receiver with Auxiliary Path and Adaptive Self-Interference Cancellation
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11571/1425315
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