Mach-Zehnder Modulator Driver Designs in 28 nm CMOS Technology for Coherent Optical Systems

Since the beginning of the Internet, the number of connected devices has experienced an exponential growth. While increasing in users number, also a huge number of services and applications have been made available through the network. The forecasts tell us that we are still at the beginning of this journey, even if the numbers are already extremely high. In order to satisfy these demands, always more capable networks have been developed. Optical links have been proven to be the best candidates for long reach backbone connections, given the low losses introduced. The final target of a link is to deliver the highest amount of data for a given bit error rate (BER). So, coherent modulations move towards this direction, providing better spectral efficiency compared to other schemes. Quadrature Phase Shift Keying (QPSK) and Quadrature Amplitude Modulation (QAM) can be exploited, but linearity and phase accuracy become crucial both for the electrical and optical portion of the system. Electro-optical modulators (EOM) are used to combine laser beams with different amplitudes and phases, to provide such complex schemes. CMOS technology is not so widely used in coherent applications, mainly because of the higher break-down voltage and gm/ID of BiCMOS devices. Yet CMOS has some interesting features, such as scalability and integration between analog and digital circuits, that might result in a reduction of the overall system costs. Furthermore, in the latest technology nodes, p- and n-type MOS transistors have very similar performance, making available complementary structures which can compensate the poor MOS transconductance efficiency. The required electrical signal at the EOM input should be large enough to fully steer the light phase, linear to preserve phase and amplitude, and broad-band to achieve the highest bitrate. This thesis reports two CMOS designs. A first driver has been designed, fabricated and tested. The proposed structure is a four stages chain, with two gain blocks, a pre-driver and a main driver. To reach good linearity, cascoded pseudo-differential structures have been implemented, apart for the pre-driver. The cascode transistor allows to bias the common source (CS) in triode region, resulting in a linear voltage-to-current conversion. Working in triode region means a lower transistor gm, and a strong dependence between transconductance and drain-to-source voltage. In this way gain variability can be introduced changing the cascode voltage. The pre-driver is a pn source follower, which feeds the main driver without impairing the gain at high frequency. This solution is capable to provide an output voltage of 1.5 Vpp-diff, with a total harmonic distortion (THD) lower than 1.8%. The gain variation over frequency is always below 3 dB up to 58 GHz. A second design has been realized and sent for fabrication, but at the moment of this dissertation not yet available. The first stage of this design is a transconductor, which provides voltage-to-current conversion. Since the involved amplitude is small, the amount of distortion introduced (which is proportional to the voltage swing) is very low. Part of the gain is provided in current domain through a current mirror-like structure, allowing, at least in principle, self cancellation of spurious components. Then, the output current-to-voltage conversion is realized with a closed-loop transimpedance amplifier (TIA). This solution intends to exploit loop gain (Gloop) in order to reduce the distortion. At the same time, a loop designed with a phase margin (PM) lower than 60°, results in high frequency peak for the closed-loop transfer function. The simulated THD for a 1.5 Vpp-diff output signal is frequency dependent, and it ranges from 0.3% at 1 GHz, up to 2% at 9 GHz. Ripples in the transfer function are below 3 dB up to 51 GHz, for all the gain configurations.