CINECA IRIS Institutional Research Information System
IRIS è la soluzione IT che facilita la raccolta e la gestione dei dati relativi alle attività e ai prodotti della ricerca. Fornisce a ricercatori, amministratori e valutatori gli strumenti per monitorare i risultati della ricerca, aumentarne la visibilità e allocare in modo efficace le risorse disponibili.
EnglishIn this paper we describe DPFPA (Double Precision Floating Point Accelerator), a FPGA-based coprocessor interfaced to the CPU through standard bus connections; it is conceived to accelerate double precision floating point operations, featuring two double precision floating point units, a pipelined adder and a pipelined multiplier with a suitable number of stages. We tested its performance by implementing a Montecarlo-Metropolis simulation of a dipolar system, using a proper software development environment designed and realized in our laboratory. DPFPA can provide a speed-up equal to 4, with respect last generation PC, showing also a good scalability in terms of clock frequency, memory capability and number of computing units
Scheda prodotto non validato
Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo
| Titolo: | High performance computing through SoC coprocessors | |
| Autori: | ||
| Data di pubblicazione: | 2010 | |
| Rivista: | ||
| Abstract: | In this paper we describe DPFPA (Double Precision Floating Point Accelerator), a FPGA-based coprocessor interfaced to the CPU through standard bus connections; it is conceived to accelerate double precision floating point operations, featuring two double precision floating point units, a pipelined adder and a pipelined multiplier with a suitable number of stages. We tested its performance by implementing a Montecarlo-Metropolis simulation of a dipolar system, using a proper software development environment designed and realized in our laboratory. DPFPA can provide a speed-up equal to 4, with respect last generation PC, showing also a good scalability in terms of clock frequency, memory capability and number of computing units | |
| Handle: | http://hdl.handle.net/11571/148515 | |
| Appare nelle tipologie: | 1.1 Articolo in rivista |
File in questo prodotto:
Copyright © 2021