This work describes the architecture and the experimental results from the characterization of a 32-channel mixed-signal application-specific integrated circuit (ASIC) developed for the readout of the lithium-drifted silicon (Si(Li)), detectors of the general antiparticle spectrometer (GAPS) experiment dedicated to searching for dark matter. The instrument is designed for the identification of antiprotons, antideuterons, and antihelium nuclei from cosmic rays during an Antarctic balloon mission scheduled for late 2024. A full-custom integrated circuit, named SLIDER32 (32-channel Si-Li detector readout) ASIC, has been produced in a commercial 180-nm CMOS technology. The ASIC comprises 32 low-noise analog readout channels featuring dynamic signal compression to comply with the wide input range, an 11-bit successive approximation register (SAR) analog-to-digital converter (ADC), and a digital back-end section which is responsible for channel setting and for sending digital information to the data acquisition system (DAQ). The circuit design criteria and the experimental results are discussed in this article.
A 32-Channel Readout ASIC for X-Ray Spectrometry and Tracking in the GAPS Experiment
Ratti L.;
2024-01-01
Abstract
This work describes the architecture and the experimental results from the characterization of a 32-channel mixed-signal application-specific integrated circuit (ASIC) developed for the readout of the lithium-drifted silicon (Si(Li)), detectors of the general antiparticle spectrometer (GAPS) experiment dedicated to searching for dark matter. The instrument is designed for the identification of antiprotons, antideuterons, and antihelium nuclei from cosmic rays during an Antarctic balloon mission scheduled for late 2024. A full-custom integrated circuit, named SLIDER32 (32-channel Si-Li detector readout) ASIC, has been produced in a commercial 180-nm CMOS technology. The ASIC comprises 32 low-noise analog readout channels featuring dynamic signal compression to comply with the wide input range, an 11-bit successive approximation register (SAR) analog-to-digital converter (ADC), and a digital back-end section which is responsible for channel setting and for sending digital information to the data acquisition system (DAQ). The circuit design criteria and the experimental results are discussed in this article.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
