This thesis introduces a new Full-Duplex (FD) architecture for mobile communication standards, eliminating the need for external Surface Acoustic Wave (SAW) filters. It starts with a review of standard requirements, an analysis of overall architecture constraints and presentation of simulation results, this work proposes a two-path noise-cancelling architecture. In this architecture, the main receiver captures the input signal from the antenna, while the auxiliary receiver captures noise leakage from the transmitter. The noise cancellation is performed in the digital domain through an adaptive digital filter. A main receiver topology based on a positive translational feedback loop is chosen for its excellent attributes, including high linearity and low noise. The forward path includes a low-noise transconductance amplifier (LNTA), four phase passive mixers and third-order filtering transimpedance amplifiers. A tunable RC feedback path is loaded at the baseband output, followed by additional four-phase passive up-conversion mixers, enabling tunable, frequency-selective input matching. An analytical model of the structure alongside measurement results will be provided in the dedicated chapter. The auxiliary receiver is designed specifically to increase the ratio between its compression point and its noise figure, with minimal power consumption. The architecture chosen is a LNTA-first with a second-order baseband filter. Thanks to the high input impedance of this receiver it can be placed at the transmitter output without adding considerable loading effects. Measurement results of this auxiliary receiver are presented at the end of the chapter. For the observation of noise cancellation, a Field-Programmable Gate Array (FPGA) is programmed in order to acquire signals from the receivers. The design includes a Clock and Data Recovery (CDR) module, a storage memory and a Universal Asynchronous Receiver-Transmitter (UART) interface for signal transmission to a computer. The design is subsequently validated, demonstrating signal cancellation in MATLAB through the use of an adaptive digital filter employing the Least Mean Squares (LMS) algorithm.

This thesis introduces a new Full-Duplex (FD) architecture for mobile communication standards, eliminating the need for external Surface Acoustic Wave (SAW) filters. It starts with a review of standard requirements, an analysis of overall architecture constraints and presentation of simulation results, this work proposes a two-path noise-cancelling architecture. In this architecture, the main receiver captures the input signal from the antenna, while the auxiliary receiver captures noise leakage from the transmitter. The noise cancellation is performed in the digital domain through an adaptive digital filter. A main receiver topology based on a positive translational feedback loop is chosen for its excellent attributes, including high linearity and low noise. The forward path includes a low-noise transconductance amplifier (LNTA), four phase passive mixers and third-order filtering transimpedance amplifiers. A tunable RC feedback path is loaded at the baseband output, followed by additional four-phase passive up-conversion mixers, enabling tunable, frequency-selective input matching. An analytical model of the structure alongside measurement results will be provided in the dedicated chapter. The auxiliary receiver is designed specifically to increase the ratio between its compression point and its noise figure, with minimal power consumption. The architecture chosen is a LNTA-first with a second-order baseband filter. Thanks to the high input impedance of this receiver it can be placed at the transmitter output without adding considerable loading effects. Measurement results of this auxiliary receiver are presented at the end of the chapter. For the observation of noise cancellation, a Field-Programmable Gate Array (FPGA) is programmed in order to acquire signals from the receivers. The design includes a Clock and Data Recovery (CDR) module, a storage memory and a Universal Asynchronous Receiver-Transmitter (UART) interface for signal transmission to a computer. The design is subsequently validated, demonstrating signal cancellation in MATLAB through the use of an adaptive digital filter employing the Least Mean Squares (LMS) algorithm.

5G SAW-less FDD architecture design

LECCHI, SIMONE
2024-06-27

Abstract

This thesis introduces a new Full-Duplex (FD) architecture for mobile communication standards, eliminating the need for external Surface Acoustic Wave (SAW) filters. It starts with a review of standard requirements, an analysis of overall architecture constraints and presentation of simulation results, this work proposes a two-path noise-cancelling architecture. In this architecture, the main receiver captures the input signal from the antenna, while the auxiliary receiver captures noise leakage from the transmitter. The noise cancellation is performed in the digital domain through an adaptive digital filter. A main receiver topology based on a positive translational feedback loop is chosen for its excellent attributes, including high linearity and low noise. The forward path includes a low-noise transconductance amplifier (LNTA), four phase passive mixers and third-order filtering transimpedance amplifiers. A tunable RC feedback path is loaded at the baseband output, followed by additional four-phase passive up-conversion mixers, enabling tunable, frequency-selective input matching. An analytical model of the structure alongside measurement results will be provided in the dedicated chapter. The auxiliary receiver is designed specifically to increase the ratio between its compression point and its noise figure, with minimal power consumption. The architecture chosen is a LNTA-first with a second-order baseband filter. Thanks to the high input impedance of this receiver it can be placed at the transmitter output without adding considerable loading effects. Measurement results of this auxiliary receiver are presented at the end of the chapter. For the observation of noise cancellation, a Field-Programmable Gate Array (FPGA) is programmed in order to acquire signals from the receivers. The design includes a Clock and Data Recovery (CDR) module, a storage memory and a Universal Asynchronous Receiver-Transmitter (UART) interface for signal transmission to a computer. The design is subsequently validated, demonstrating signal cancellation in MATLAB through the use of an adaptive digital filter employing the Least Mean Squares (LMS) algorithm.
27-giu-2024
This thesis introduces a new Full-Duplex (FD) architecture for mobile communication standards, eliminating the need for external Surface Acoustic Wave (SAW) filters. It starts with a review of standard requirements, an analysis of overall architecture constraints and presentation of simulation results, this work proposes a two-path noise-cancelling architecture. In this architecture, the main receiver captures the input signal from the antenna, while the auxiliary receiver captures noise leakage from the transmitter. The noise cancellation is performed in the digital domain through an adaptive digital filter. A main receiver topology based on a positive translational feedback loop is chosen for its excellent attributes, including high linearity and low noise. The forward path includes a low-noise transconductance amplifier (LNTA), four phase passive mixers and third-order filtering transimpedance amplifiers. A tunable RC feedback path is loaded at the baseband output, followed by additional four-phase passive up-conversion mixers, enabling tunable, frequency-selective input matching. An analytical model of the structure alongside measurement results will be provided in the dedicated chapter. The auxiliary receiver is designed specifically to increase the ratio between its compression point and its noise figure, with minimal power consumption. The architecture chosen is a LNTA-first with a second-order baseband filter. Thanks to the high input impedance of this receiver it can be placed at the transmitter output without adding considerable loading effects. Measurement results of this auxiliary receiver are presented at the end of the chapter. For the observation of noise cancellation, a Field-Programmable Gate Array (FPGA) is programmed in order to acquire signals from the receivers. The design includes a Clock and Data Recovery (CDR) module, a storage memory and a Universal Asynchronous Receiver-Transmitter (UART) interface for signal transmission to a computer. The design is subsequently validated, demonstrating signal cancellation in MATLAB through the use of an adaptive digital filter employing the Least Mean Squares (LMS) algorithm.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11571/1500140
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