This brief presents a fast transient LDO with high power supply rejection ratio (PSRR) over 100-kHz based on adaptive biasing, dynamic biasing technique and a current mode feed-forward amplifier (CMFFA). The dynamic biasing improves the load transient response and the adaptive biasing benefits the loop stability. The CMFFA introduces a left-half-plane zero to compensate for the non-dominant pole without large current consumption. Moreover, a impedance adaptive circuit is also used in this design: it ensures the DC gain and pushes a non-dominant pole to high frequency. Through these methods, the proposed LDO is stable over full load range, from 0mA to 150mA, it achieves fast transient response and high PSRR with a low quiescent current. The LDO is fabricated in a 0.6- mu m CMOS technology. The output voltage can be regulated from 1.8V to 3.3V and the load capacitance is 1 mu F. For a 150mA load step and a 3.3V output voltage, the maximum undershoot voltage is 38.6mV. At maximum load condition, a 41dB PSRR is achieved at 100-kHz and the loop gain bandwidth product is 1.9MHz. The DC gain is around 70dB over the full load range. The measured load regulation and line regulation are 0.06mV/mA and 1mV/V, respectively. The LDO has a minimum quiescent current of 9.6 mu A without load. Finally, the proposed LDO achieves a FOM1 of 16.47ps and a FOM2 of 123.52 mu V.
A Fast Transient LDO Regulator Featuring High PSRR Over 100-kHz Frequency Range With Adaptive, Dynamic Biasing, and Current Mode Feed-Forward Amplifier
Bonizzoni, Edoardo
2024-01-01
Abstract
This brief presents a fast transient LDO with high power supply rejection ratio (PSRR) over 100-kHz based on adaptive biasing, dynamic biasing technique and a current mode feed-forward amplifier (CMFFA). The dynamic biasing improves the load transient response and the adaptive biasing benefits the loop stability. The CMFFA introduces a left-half-plane zero to compensate for the non-dominant pole without large current consumption. Moreover, a impedance adaptive circuit is also used in this design: it ensures the DC gain and pushes a non-dominant pole to high frequency. Through these methods, the proposed LDO is stable over full load range, from 0mA to 150mA, it achieves fast transient response and high PSRR with a low quiescent current. The LDO is fabricated in a 0.6- mu m CMOS technology. The output voltage can be regulated from 1.8V to 3.3V and the load capacitance is 1 mu F. For a 150mA load step and a 3.3V output voltage, the maximum undershoot voltage is 38.6mV. At maximum load condition, a 41dB PSRR is achieved at 100-kHz and the loop gain bandwidth product is 1.9MHz. The DC gain is around 70dB over the full load range. The measured load regulation and line regulation are 0.06mV/mA and 1mV/V, respectively. The LDO has a minimum quiescent current of 9.6 mu A without load. Finally, the proposed LDO achieves a FOM1 of 16.47ps and a FOM2 of 123.52 mu V.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
