This article presents a shunt-based current sensor (CS) designed for brushless dc (BLDC) motor control. The proposed sensing system digitizes the current flowing through an external 12-mΩ resistor by sampling the resulting voltage drop by means of an accumulation-based sample-and-hold (S/H) circuit followed by a SAR-assisted Σ∆ incremental analog-to-digital converter (ADC). The employment of an accumulation technique within the S/H circuit allows to amplify the input signal while effectively mitigating the kT/C noise contribution, leading to a significant improvement to the dynamic range (DR) of the readout. The proposed ADC architecture, on the other hand, allows achieving the target resolution in a relatively fast conversion time, essential feature needed to meet the stringent latency requirement imposed by the considered application. The sensor was fabricated in a standard 130-nm CMOS process, occupies a silicon area of 0.4 mm2, and draws 6.7 mA from a 1.5-V supply. Over a ±4-A input current range and a -20 °C to 100 °C temperature range, it achieves a worst case gain error of ±0.8%. Moreover, the sensor features a DR of 78.2 dB and a 2.75-µs conversion time, resulting in a state-of-the-art 0.21-fW/Hz figure of merit (FoM).
A 78.2-dB Dynamic Range Shunt-Based Current Sensor for BLDC Motor Control With 2.75-μs Conversion Time and 0.4-mm2 Active Area
Aprile A.
;Yarragunta J. S.;Bonizzoni E.;Malcovati P.
2025-01-01
Abstract
This article presents a shunt-based current sensor (CS) designed for brushless dc (BLDC) motor control. The proposed sensing system digitizes the current flowing through an external 12-mΩ resistor by sampling the resulting voltage drop by means of an accumulation-based sample-and-hold (S/H) circuit followed by a SAR-assisted Σ∆ incremental analog-to-digital converter (ADC). The employment of an accumulation technique within the S/H circuit allows to amplify the input signal while effectively mitigating the kT/C noise contribution, leading to a significant improvement to the dynamic range (DR) of the readout. The proposed ADC architecture, on the other hand, allows achieving the target resolution in a relatively fast conversion time, essential feature needed to meet the stringent latency requirement imposed by the considered application. The sensor was fabricated in a standard 130-nm CMOS process, occupies a silicon area of 0.4 mm2, and draws 6.7 mA from a 1.5-V supply. Over a ±4-A input current range and a -20 °C to 100 °C temperature range, it achieves a worst case gain error of ±0.8%. Moreover, the sensor features a DR of 78.2 dB and a 2.75-µs conversion time, resulting in a state-of-the-art 0.21-fW/Hz figure of merit (FoM).I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
