In this paper, a Noise-Shaping Successive Approximation Register (NS-SAR) Analog-to-Digital Converter (ADC) optimized for low-power Audio Activity Detection (AAD) is presented. Based on a 5-bits bottom-sampled CDAC synchronous SAR architecture, the proposed converter exploits a second-order error-feedback loop filter and a fully passive Charge-Sharing (CS) summing node to enhance the final resolution and improve power efficiency. An open-loop Process-Voltage-Temperature (PVT) insensitive amplifier is employed in the feedback loop to compensate for the CS losses, ensuring a 78-dB dynamic range and a 165.3-dB Schreier Figure-of-Merit (FoMs) of the converter. Fabricated in a 65-nm BCD process, the ADC core occupies only 0.129 mm2 and consumes 14.9 µW from a 1.2-V supply.
A Quasi-Passive 78-dB DR 14.9-W Noise-Shaping SAR A/D Converter for Audio Activity Detection Applications
Tambussi, Marco;Grassi, Marco;Bonizzoni, Edoardo;Malcovati, Piero
2025-01-01
Abstract
In this paper, a Noise-Shaping Successive Approximation Register (NS-SAR) Analog-to-Digital Converter (ADC) optimized for low-power Audio Activity Detection (AAD) is presented. Based on a 5-bits bottom-sampled CDAC synchronous SAR architecture, the proposed converter exploits a second-order error-feedback loop filter and a fully passive Charge-Sharing (CS) summing node to enhance the final resolution and improve power efficiency. An open-loop Process-Voltage-Temperature (PVT) insensitive amplifier is employed in the feedback loop to compensate for the CS losses, ensuring a 78-dB dynamic range and a 165.3-dB Schreier Figure-of-Merit (FoMs) of the converter. Fabricated in a 65-nm BCD process, the ADC core occupies only 0.129 mm2 and consumes 14.9 µW from a 1.2-V supply.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
