A monolithic digital Silicon Photomultiplier (SiPM) featuring 1024 microcells with a 30-micrometer pitch and a 50% fill factor has been designed in a 110-nanometer CMOS image sensor technology. The device under consideration integrates both SPAD sensors and front-end electronics in the same substrate. It can count up to 1024 photons in less than 22 ns, while assigning timestamps to the first and last detected photons with a time resolution of less than 100 ps. A parallel counter structure combined with a fast adder tree provides photon counting in digital form with low latency, whereas a carefully balanced fast NAND tree ensures a fixed-pattern time uncertainty not exceeding 26 ps. The architecture incorporates in-pixel memory for individual cell disabling and configurable thresholding on the timing signal for noise mitigation. In order to optimize the fill factor, a part of the electronics is placed outside the array, while the most sensitive elements of the timing and counting circuits are laid out close to the sensor, in the SPAD array. A serial readout is employed to provide a single output connection per SiPM, thereby simplifying system integration.

Ultra-Fast Digital Silicon Photomultiplier with Timestamping Capability in a 110 nm CMOS Process

Floris, Tommaso Maria;Ratti, Lodovico;Shojaei, Fatemeh;Vacchi, Carla
2026-01-01

Abstract

A monolithic digital Silicon Photomultiplier (SiPM) featuring 1024 microcells with a 30-micrometer pitch and a 50% fill factor has been designed in a 110-nanometer CMOS image sensor technology. The device under consideration integrates both SPAD sensors and front-end electronics in the same substrate. It can count up to 1024 photons in less than 22 ns, while assigning timestamps to the first and last detected photons with a time resolution of less than 100 ps. A parallel counter structure combined with a fast adder tree provides photon counting in digital form with low latency, whereas a carefully balanced fast NAND tree ensures a fixed-pattern time uncertainty not exceeding 26 ps. The architecture incorporates in-pixel memory for individual cell disabling and configurable thresholding on the timing signal for noise mitigation. In order to optimize the fill factor, a part of the electronics is placed outside the array, while the most sensitive elements of the timing and counting circuits are laid out close to the sensor, in the SPAD array. A serial readout is employed to provide a single output connection per SiPM, thereby simplifying system integration.
2026
The Electrical and Electronics Engineering category covers resources concerned with applications of electricity, generally those involving current flow through conductors, as in motors and generators. This category also covers the examination of the conduction of electricity through gases or a vacuum as well as through semiconducting materials. Topics include image and signal processing, electromagnetics, electronic components and materials, microwave technology, and microelectronics.
Esperti anonimi
Inglese
Internazionale
ELETTRONICO
15
6
CMOS SPAD; digital SiPM; fast timing; monolithic sensors; photon counting
14
info:eu-repo/semantics/article
262
Floris, Tommaso Maria; Campajola, Marcello; Collazuol, Gianmaria; Da Rocha Rolo, Manuel Dionísio; Fiorillo, Giuliana; Licciulli, Francesco; Mazziotta,...espandi
1 Contributo su Rivista::1.1 Articolo in rivista
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11571/1548828
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