Analysis and Design of a Dual-Core D-Band Colpitts Oscillator With 150-GHz Third-Harmonic Extraction in 22-nm CMOS FD-SOI

This article presents a dual-core oscillator with third-harmonic extraction at 150 GHz. The oscillator is built around a Colpitts topology, leveraging the harmonic-rich transistor drain current for its extraction. The addition of a transformer-based resonator boosts the loop gain, allowing for a reduction of the transistor size and parasitics while peaking the impedance at the third harmonic of the fundamental oscillation frequency. Small- and large-signal circuit analyses are presented in this article to derive guidelines for design optimization. Two oscillator cores are also coupled for 3-dB phase noise improvement. Magnetic coupling in the resonators is exploited for coupling, leading to a simple layout without extra parasitic elements and good robustness to mismatches. A test chip is designed and fabricated in Global Foundries 22-nm CMOS fully depleted silicon-on-insulator (FDSOI) technology. The fundamental oscillation frequency is tunable from 47.5 to 51.5 GHz, and the third harmonic is extracted from 142.5 to 154.5 GHz. With 25.6 mW from 0.8-V voltage supply, the measured phase noise at 1-MHz offset at 154.5 GHz is -87.4 dBc/Hz, corresponding to -177.1-dBc/Hz figure-of-merit (FoM). To the best of our knowledge, this work demonstrates the lowest phase noise and the best FoM among reported CMOS oscillators delivering a signal in the same frequency range.