This article proposes a novel zero-pole doublet compensation method for a three-stage operational transconductance amplifier (OTA) used in high-linearity transimpedance amplifiers (TIAs). In the proposed OTA, the first stage employs a switched-capacitor (SC) amplifier, enabling independent and precise control over the frequency locations of the zero-pole doublet. The subsequent second and third stages are formed by a Miller-compensated amplifier incorporating positive feedback, which provides high gain and establishes a high-frequency dominant pole. The proposed compensation method can effectively enhance the gain-bandwidth (GBW) product of the OTA by ten times, resulting in a high input third-order intercept point (IIP3). The designed TIA, fabricated in a 22-nm CMOS process, provides a gain of 5.1 dB with a bandwidth of 20 MHz, and an input-referred noise of 48μ V (normalized to 10 MHz) with an IIP3 of 43.3 dBm and a 1-dB compression point of 8.3 dBm. The TIA occupies an area of 0.024 mm2 and consumes 4.9 mW from a 1.8-V supply voltage.
A +43.3-dBm IIP3, Low-Power Transimpedance Amplifier Employing a Switched-Capacitor Amplifier-Based Transition-Band Pole-Zero Doublets Compensation Technique
Jin J.;Manstretta D.;
2026-01-01
Abstract
This article proposes a novel zero-pole doublet compensation method for a three-stage operational transconductance amplifier (OTA) used in high-linearity transimpedance amplifiers (TIAs). In the proposed OTA, the first stage employs a switched-capacitor (SC) amplifier, enabling independent and precise control over the frequency locations of the zero-pole doublet. The subsequent second and third stages are formed by a Miller-compensated amplifier incorporating positive feedback, which provides high gain and establishes a high-frequency dominant pole. The proposed compensation method can effectively enhance the gain-bandwidth (GBW) product of the OTA by ten times, resulting in a high input third-order intercept point (IIP3). The designed TIA, fabricated in a 22-nm CMOS process, provides a gain of 5.1 dB with a bandwidth of 20 MHz, and an input-referred noise of 48μ V (normalized to 10 MHz) with an IIP3 of 43.3 dBm and a 1-dB compression point of 8.3 dBm. The TIA occupies an area of 0.024 mm2 and consumes 4.9 mW from a 1.8-V supply voltage.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
