Generation and Distribution of Low-Jitter Clock Signals for SerDes Applications

In the last 20 years, electro-optical communications have been developing more challeng ing requests, halving specifications on noise and power each year. As any electrical cir cuit would have efficiency and speed limits, it’s crucial to quantify and improve as much as possible such performance in every application. It becomes even more important in SerDes (Serializer-Deserializer) transceivers as they implement the wire enabling people to connect, store and access data, which are everyday activities, necessary for most jobs, errands and leisure. Recently, this need appeared even more evident with the advent of 5G and Internet of Things (IoT). Being clock about half the total power consumption in VLSI chips, it is fundamental to optimize the clock signal generation and distribution. In this thesis, clock in transmitters PLL will be dealt with. In particular, clock distribution becomes a huge design aspect for large chips, whose lengths span from 1mm to 10mm. Distribution usually requires half the power consumption and adds up noise as well, thus the focus of this work is to optimize the clock management through a distributed oscillator architecture. The traditional trade-off power-phase noise (PN) is examined and a new solution is proposed through in-phase coupling [1]. This thesis is organised into six parts: first a brief introduction, which will deal with the specific application and the main difference between a stand alone and a distributed oscillator, i.e., the solution pro posed in this work, followed by a first chapter about the state of the art by providing an oscillator panoramic and some information about the main oscillators metrics, such as PN and FoM, and their main characteristics. After these introductory parts, further details are provided about coupled oscillators, in particular specifying how the coupling mechanism works and how to deal with coupling main issues, for example FoM penalty and mode stability. First, these issues will be addressed for a simplified dual-core sys tem, then a solution for the same problems is presented for a four-core oscillator. In the third chapter, the proposed architecture is introduced, with a focus on the adopted Fin FET technology and some layout information. In the end, the fourth chapter presents the test-chip measurements and the fifth one contains the conclusion.