Low-Noise Amplifiers for 60-GHz Wireless Communications in CMOS and BiCMOS Technologies

The continuous growth of high-speed wireless applications such as virtual reality, wireless HD video streaming, and short-range multi-gigabit data links has driven increasing interest toward millimeter-wave (mm-wave) communication systems operating in the unlicensed 60-GHz band (57–64 GHz). The large available bandwidth enables multi-Gbit/s data rates; however, the realization of compact, energy-efficient, and robust receiver front-ends at these frequencies presents significant circuit and layout challenges, including low supply voltage operation, noise optimization, impedance matching, electrostatic discharge (ESD) protection, linearity under strong blockers, and strict control of layout parasitics in advanced silicon technologies. This thesis presents the design, implementation, and experimental validation of 60-GHz integrated receiver front-end circuits in 28-nm CMOS and 130-nm SiGe BiCMOS technologies, addressing low-power/wideband operation and enhanced linearity, respectively. The first part of the thesis is focused on the design of a 60-GHz low-noise amplifier (LNA) for multigigabit/s communications in a 28-nm bulk CMOS technology by TSMC, featuring a 9-metal back-end-of-line (BEOL) stack including a 3.5-μm thick top metal layer and an Alucap option for low-loss passive integration. A pseudo-differential two-stage LNA topology is proposed as the best performance tradeoff (i.e., gain, frequency bandwidth, power consumption). Specifically, a power-efficient simultaneous noise and impedance matching (PE-SNIM ) technique is adopted together with custom-designed stacked transformers providing impedance transformation, resonance tuning, and intrinsic ESD robustness. The LNA has been integrated as a stand-alone block for direct on-wafer experimental validation, by using a 50-Ohm buffer stage. Moreover, it has been used within a complete 60-GHz receiver to drive a fully differential on-off keying/amplitude shift keying (OOK/ASK) demodulator, enabling a data rate of about 3 Gbit/s at a sensitivity of −40 dBm with total power consumption below 15 mW by using a 0.9-V supply. Both the LNA and the complete receiver have been fabricated. Experimentally characterization through on-wafer measurements has been carried out for the LNA, which confirms a correct operation around 60 GHz (with about 6% frequency drift). On the other hand, a limited validation of the OOK receiver is available, due to a lack of some instruments for high-data rate modulation at 60 GHz. The second part of the thesis focuses on linearity enhancement through the design of a highly linear 60-GHz LNA implemented in 130-nm SiGe BiCMOS technology by Infineon Technologies, characterized by a 6-metal stack and high-speed heterojunction bipolar transistors (HBTs). A novel two-path power-combining architecture is proposed, exploiting passive load redistribution and transformer-based current combining to improve large-signal performance without dynamic bias control. Post-layout simulations demonstrate up to 6-dB improvement in input 1-dB compression point (IP1dB) compared to a conventional two-stage topology, while maintaining competitive gain, NF, and moderate power consumption. The layout has been completed and verified through electromagnetic and parasitic extraction simulations, and fabrication is currently in progress. Fabricated chips could be available for on-wafer experimental validation in a few months. Overall, this work demonstrates that advanced bulk CMOS and SiGe BiCMOS technologies can effectively address complementary challenges in 60-GHz receiver design (namely low power operation in nanoscale CMOS and high linearity in SiGe BiCMOS implementations). The proposed circuit architectures and layout methodologies provide practical guidelines for the realization of compact, low-power, and blocker-tolerant mm-wave front-ends for next-generation high-data-rate wireless systems.