A fully integrated 0.18μm CMOS ΣΔ fractional synthesizer targeting 3G wireless terminals applications is presented. This work is a practical example of a more general study on frequency fractional synthesis. A simple linear model of the system is presented and used to simulate different ΣΔ modulators topologies and to evaluate the effects of circuits non-idealities particularly on output spurious tones. Phase Frequency Detector (PFD) and Charge Pump (CP) non-linearity effects are analysed in details, the obtained results are confirmed by measurement. Solutions to overcome these limitations are given. At last, a ΣΔ quantization noise compensation technique is presented allowing to break the trade-off between Phase Locked Loop (PLL) bandwidth and high frequency noise regrowth.
A 19mW 2.2GHz Fully Integrated CMOS Sigma Delta Fractional Synthesiser With 35Hz Frequency Step and Quantization Noise Compensation
CASTELLO, RINALDO
2003-01-01
Abstract
A fully integrated 0.18μm CMOS ΣΔ fractional synthesizer targeting 3G wireless terminals applications is presented. This work is a practical example of a more general study on frequency fractional synthesis. A simple linear model of the system is presented and used to simulate different ΣΔ modulators topologies and to evaluate the effects of circuits non-idealities particularly on output spurious tones. Phase Frequency Detector (PFD) and Charge Pump (CP) non-linearity effects are analysed in details, the obtained results are confirmed by measurement. Solutions to overcome these limitations are given. At last, a ΣΔ quantization noise compensation technique is presented allowing to break the trade-off between Phase Locked Loop (PLL) bandwidth and high frequency noise regrowth.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
