A Wide-Band Receiver for multi Gbit/s communications in 65nm CMOS

High rate communications technology leveraging the unlicensed spectrum around 60GHz is almost ready for deployment with several demonstrations of successful wireless links. One key aspect of the transceiver is the ability to handle analog fractional bandwidths in the order of 20%, challenging for both the linear processing chain and the frequency reference generator. In classical LC loaded stages bandwidth trades with gain making them unsuitable for wide band amplifiers at millimeter-waves where the available device gain is relatively low. In this work, we exploit inter-stage coupling realizing higher order filters where wider bandwidth is achieved at the expense of in-band gain ripple only. The receiver adopts a sliding IF architecture employing an integer-N type-II synthesizer, with a three state phase frequency detector – charge pump combination, a switched tuned LC VCO followed by a low power wide range divider chain. By judicious choice of charge pump current and filter components integrated phase noise, critical for signal constellation integrity at high rate, is kept low. This paper inspects the inter-stage coupling technique, providing design formulae, and discusses the design of each receiver block. Experiments performed on 65nm prototypes provide: 6.5dB maximum NF over >13GHz bandwidth, -22.5dBc integrated phase noise while consuming 84mW.