Wireless on-chip processing at millimeter waves still lacks key functions: quadrature generation enabling direct conversion architectures and simplifying phased-array systems, frequency division with an operating range wide enough to compensate spreads due to component variations. This paper addresses the implementation of these functions, introducing new circuit solutions. The quadrature voltage-controlled oscillator (VCO) relies on a ring of two tuned VCOs, where the oscillation frequency depends on inter-stage passive components only, demonstrating low noise and accurate quadrature phases. Prototypes, realized in 65-nm CMOS, show 56–60.4-GHz tunable oscillation frequency, phase noise better than 95 dBc/Hz at 1-MHz offset in the tuning range, 1.5 maximum phase error while consuming 22 mA from a 1-V supply. The frequency divider is based on clocked differential amplifiers, working as dynamic CML latches, achieving high speed and low power simultaneously. A divider by 4 realized in 65-nm CMOS occupies 15 m 30 m, features an operating frequency programmable from 20 to 70 GHz in nine bands and consumes 6.5 mW.

A Low-Noise Quadrature VCO Based on Magnetically Coupled Resonators and a Wideband Frequency Divider at Millimeter Waves

GHILIONI, ANDREA;MAZZANTI, ANDREA;SVELTO, FRANCESCO
2011-01-01

Abstract

Wireless on-chip processing at millimeter waves still lacks key functions: quadrature generation enabling direct conversion architectures and simplifying phased-array systems, frequency division with an operating range wide enough to compensate spreads due to component variations. This paper addresses the implementation of these functions, introducing new circuit solutions. The quadrature voltage-controlled oscillator (VCO) relies on a ring of two tuned VCOs, where the oscillation frequency depends on inter-stage passive components only, demonstrating low noise and accurate quadrature phases. Prototypes, realized in 65-nm CMOS, show 56–60.4-GHz tunable oscillation frequency, phase noise better than 95 dBc/Hz at 1-MHz offset in the tuning range, 1.5 maximum phase error while consuming 22 mA from a 1-V supply. The frequency divider is based on clocked differential amplifiers, working as dynamic CML latches, achieving high speed and low power simultaneously. A divider by 4 realized in 65-nm CMOS occupies 15 m 30 m, features an operating frequency programmable from 20 to 70 GHz in nine bands and consumes 6.5 mW.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11571/365780
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