The availability of wide-band low-power frequency dividers is fundamental in transceivers for emerging mm-wave applications. Up to date injection locked topologies have been investigated for very high frequency operations but at the price of large area and limited frequency range. In this work, we investigate a new class based on dynamic latches with load modulation. The proposed latches can be viewed as the evolution of classic static CML latches where the regenerative cross-coupled pair is removed for minimum parasitic at output nodes, i.e., maximum speed, and loads are modulated by the input clock for maximum charge retention during hold times. A time-domain circuit inspection aimed at deriving analytical expressions for maximum and minimum operation frequency and providing guidelines for optimum design is reported. Prototypes of dividers by 4, realized in 32 nm bulk CMOS, operate between 14 GHz and 70 GHz, demonstrating a fractional bandwidth in excess of 60% in the entire range, 4.8 mW of maximum power consumption and 55 ×18 μm2 occupied area.
Analysis and Design of mm-Wave Frequency Dividers Based on Dynamic Latches With Load Modulation
GHILIONI, ANDREA;MAZZANTI, ANDREA;SVELTO, FRANCESCO
2013-01-01
Abstract
The availability of wide-band low-power frequency dividers is fundamental in transceivers for emerging mm-wave applications. Up to date injection locked topologies have been investigated for very high frequency operations but at the price of large area and limited frequency range. In this work, we investigate a new class based on dynamic latches with load modulation. The proposed latches can be viewed as the evolution of classic static CML latches where the regenerative cross-coupled pair is removed for minimum parasitic at output nodes, i.e., maximum speed, and loads are modulated by the input clock for maximum charge retention during hold times. A time-domain circuit inspection aimed at deriving analytical expressions for maximum and minimum operation frequency and providing guidelines for optimum design is reported. Prototypes of dividers by 4, realized in 32 nm bulk CMOS, operate between 14 GHz and 70 GHz, demonstrating a fractional bandwidth in excess of 60% in the entire range, 4.8 mW of maximum power consumption and 55 ×18 μm2 occupied area.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
