The possibility of implementing the double-sampling (DS) techinque in infinite impulse response (IIR) first- and second-order switched-capacitor (SC) decimators is considered. The DS-SC circuits that result are designed using the same procedure as standard IIR decimators, and only a different SC implementation results with a reorganized clock phasing. The main advantage is that the time allowed for the op-amps to settle can be equal to the output sampling period rather than one half of it. Using the proposed DS decimators allows the design of high-frequency SC filtering systems (an antialiasing SC decimator filter and a `core' DS-SC filter) where the op-amp speed requirements are the same in each block