This brief presents a system architecture designed to enable 1-bit-per-cell storage in Ge-rich phase change memory (PCM) even in the presence of the resistance drift of the low-resistance (SET) state, thus overcoming the intrinsic low storage density (half bit per cell) of the currently used differential solutions. The read reference current is automatically adjusted to best exploit the reading window between the RESET and the SET state that changes over time. The working principles of the system are presented, discussed, and experimentally validated. The proposed system was implemented exploiting a 110-nm BCD embedded PCM test chip and successfully tested in the temperature range from -40 °C to +150 °C.
Current tracking technique enabling 1-bit/cell storage in Ge-rich phase change memory
Zurla R.
;Cabrini A.;Volpe F.;Torelli G.
2019-01-01
Abstract
This brief presents a system architecture designed to enable 1-bit-per-cell storage in Ge-rich phase change memory (PCM) even in the presence of the resistance drift of the low-resistance (SET) state, thus overcoming the intrinsic low storage density (half bit per cell) of the currently used differential solutions. The read reference current is automatically adjusted to best exploit the reading window between the RESET and the SET state that changes over time. The working principles of the system are presented, discussed, and experimentally validated. The proposed system was implemented exploiting a 110-nm BCD embedded PCM test chip and successfully tested in the temperature range from -40 °C to +150 °C.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
