N-and P-type transistors from a 14 nm finFET technology have been tested from the standpoint of static current-voltage characteristics, small signal parameters and noise properties in view of analog front-end applications. Device electrical features are found to be compliant with the scaling trend as carried on with planar CMOS technologies. Comparison with standard, less scaled bulk CMOS processes points out that transition from planar, single-gate to vertical, multiple-gate structures does not affect significantly the device analog performance. The paper will focus in particular on the noise properties of the transistors, featuring different gate length and width and operated in the weak to moderate inversion region.

Analog front-end design perspective of a 14 nm finFET technology

Ratti L.;
2019-01-01

Abstract

N-and P-type transistors from a 14 nm finFET technology have been tested from the standpoint of static current-voltage characteristics, small signal parameters and noise properties in view of analog front-end applications. Device electrical features are found to be compliant with the scaling trend as carried on with planar CMOS technologies. Comparison with standard, less scaled bulk CMOS processes points out that transition from planar, single-gate to vertical, multiple-gate structures does not affect significantly the device analog performance. The paper will focus in particular on the noise properties of the transistors, featuring different gate length and width and operated in the weak to moderate inversion region.
978-1-7281-4164-0
File in questo prodotto:
Non ci sono file associati a questo prodotto.

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11571/1349026
Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 1
  • ???jsp.display-item.citation.isi??? 0
social impact