An Application Specific Instruction-set Processor (ASIP) for the realization of Hard Disk Drive Regular Servo Sequencer (RSS) and the related firmware for its reconfiguration is presented. The proposed architecture is a 12 bit Reduced Instruction Set Computer (RISC) processor with 32 registers, Harvard architecture memory and 19 I/O ports. The Instruction Set has been customized to Regular Servo Sequencer. The firmware can reconfigure the Microprogrammed Servo Sequencer (MSS): it’s possible to initialize registers and instruction memory and to reconfigure the port mapping. The target is to gain more flexibility than hardwired Regular Servo Sequencer, but at the same time to maintain the same performance in terms of elaboration frequency. The performance of the proposed architecture achieved by cell-based synthesis software is reported.
Implementation of microprogrammed hard disk drive servosequencer
BALDRIGHI, PAOLA;MAGGI, MARCO MAURIZIO;CASTELLANO, MARCO;VACCHI, CARLA;
2008-01-01
Abstract
An Application Specific Instruction-set Processor (ASIP) for the realization of Hard Disk Drive Regular Servo Sequencer (RSS) and the related firmware for its reconfiguration is presented. The proposed architecture is a 12 bit Reduced Instruction Set Computer (RISC) processor with 32 registers, Harvard architecture memory and 19 I/O ports. The Instruction Set has been customized to Regular Servo Sequencer. The firmware can reconfigure the Microprogrammed Servo Sequencer (MSS): it’s possible to initialize registers and instruction memory and to reconfigure the port mapping. The target is to gain more flexibility than hardwired Regular Servo Sequencer, but at the same time to maintain the same performance in terms of elaboration frequency. The performance of the proposed architecture achieved by cell-based synthesis software is reported.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
