The implementation of an unclocked DFE (UC-DFE) architecture for high-speed PAM-4 signals is investigated in this brief. Instead of clocked slicers and flip-flops, data-decision and feedback delay control are performed by saturated analog delay chains. As a result, the UC-DFE, previously exploited for NRZ signals, saves power consumption and silicon area while the simple implementation allows operation at high data-rate. A receiver front-end comprising a linear equalizer and the proposed 2-tap UC-DFE scheme is designed in 7 nm FinFET technology. From post-layout simulations, the receiver recovers a PAM-4 signal at 112 Gb/s after an 18 dB loss channel with a power efficiency of 0.47 pJ/bit. The receiver also works with NRZ signals at half the bit-rate equalizing 24 dB channel loss with a power efficiency of 0.70 pJ/bit.

A 112 Gb/s PAM-4 RX Front-End with Unclocked Decision Feedback Equalizer

Petricli I.;Zhang H.;Monaco E.;Mazzanti A.
2021

Abstract

The implementation of an unclocked DFE (UC-DFE) architecture for high-speed PAM-4 signals is investigated in this brief. Instead of clocked slicers and flip-flops, data-decision and feedback delay control are performed by saturated analog delay chains. As a result, the UC-DFE, previously exploited for NRZ signals, saves power consumption and silicon area while the simple implementation allows operation at high data-rate. A receiver front-end comprising a linear equalizer and the proposed 2-tap UC-DFE scheme is designed in 7 nm FinFET technology. From post-layout simulations, the receiver recovers a PAM-4 signal at 112 Gb/s after an 18 dB loss channel with a power efficiency of 0.47 pJ/bit. The receiver also works with NRZ signals at half the bit-rate equalizing 24 dB channel loss with a power efficiency of 0.70 pJ/bit.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11571/1410417
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