This paper proposes a dual ramp, pulse position modulation analog-to-digital converter. A delay cell is proposed in this work, which converts the timing information into a thermometric code. The proposed architecture uses a dual ramp, which initiates the time to digital quantization from both Most Significant Bit (MSB) and Least Significant Bit (LSB) ends. It requires the use of two current sources at both the ends resulting in more symmetrical non-linearity behavior compared to single-ramp architecture, thus improving the INL of the ADC. This technique leads to an increase in the sampling frequency by a factor of 2. It is designed and implemented in a 65-nm CMOS technology with a supply voltage of 1-V. The proposed ADC achieves an effective number of bits of 4.49 bits at a sampling rate of 100 MHz.

A 1-V, 5-bit, 180-µW, differential pulse position modulation ADC in 65-nm CMOS process

Bonizzoni E.
2021

Abstract

This paper proposes a dual ramp, pulse position modulation analog-to-digital converter. A delay cell is proposed in this work, which converts the timing information into a thermometric code. The proposed architecture uses a dual ramp, which initiates the time to digital quantization from both Most Significant Bit (MSB) and Least Significant Bit (LSB) ends. It requires the use of two current sources at both the ends resulting in more symmetrical non-linearity behavior compared to single-ramp architecture, thus improving the INL of the ADC. This technique leads to an increase in the sampling frequency by a factor of 2. It is designed and implemented in a 65-nm CMOS technology with a supply voltage of 1-V. The proposed ADC achieves an effective number of bits of 4.49 bits at a sampling rate of 100 MHz.
978-1-7281-9201-7
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11571/1445421
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