This work is concerned with the design of Charge Sensitive Amplifiers (CSAs) featuring dynamic signal compression. Two different CSA variants have been developed to reach low-noise performance while dealing with signals covering more than three decades in dynamic range. The CSAs have been designed in a 65 nm CMOS technology as part of the front-end circuit for the readout of Low Gain Avalanche Diodes (LGADs) based particle detectors for the next generation of space-borne experiments. The paper will discuss the proposed CSA architectures and the relevant simulation results.
Charge Sensitive Amplifiers with Bi- and Trilinear Signal Compression Feature for LGAD Detectors
Giroletti, S;Ratti, L;Vacchi, C
2023-01-01
Abstract
This work is concerned with the design of Charge Sensitive Amplifiers (CSAs) featuring dynamic signal compression. Two different CSA variants have been developed to reach low-noise performance while dealing with signals covering more than three decades in dynamic range. The CSAs have been designed in a 65 nm CMOS technology as part of the front-end circuit for the readout of Low Gain Avalanche Diodes (LGADs) based particle detectors for the next generation of space-borne experiments. The paper will discuss the proposed CSA architectures and the relevant simulation results.File in questo prodotto:
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