This paper proposes a time-domain-based architecture for implementing a bandgap reference: indeed, the proportional-to-absolute-temperature (PTAT) voltage is provided by subtracting the gate-to-source voltages (VGS) generated in two subsequent phases by the same diode-connected NMOS device, operating in subthreshold region and biased at different currents. As the same transistor is employed in both phases for the PTAT voltage generation, mismatch effects are inherently reduced. The proposed bandgap reference combines the PTAT and the complementary-to-absolute-temperature (CTAT) voltages by means of a switched capacitor difference amplifier and, if required, includes a dedicated sampling and filtering circuit. It features 5-bits trimming and implements curvature compensation through the addition of an integrated resistor with appropriate temperature dependence to the CTAT branch. The proposed bandgap reference circuit was designed in a standard 130-nm CMOS process and was extensively simulated in Cadence Virtuoso, achieving a worst-case 0.756-ppm/degrees C temperature coefficient.

A 0.756-ppm/°C Time-Domain-Based Curvature-Compensated Bandgap Reference

Moisello, E
;
Bonizzoni, E;Malcovati, P
2023-01-01

Abstract

This paper proposes a time-domain-based architecture for implementing a bandgap reference: indeed, the proportional-to-absolute-temperature (PTAT) voltage is provided by subtracting the gate-to-source voltages (VGS) generated in two subsequent phases by the same diode-connected NMOS device, operating in subthreshold region and biased at different currents. As the same transistor is employed in both phases for the PTAT voltage generation, mismatch effects are inherently reduced. The proposed bandgap reference combines the PTAT and the complementary-to-absolute-temperature (CTAT) voltages by means of a switched capacitor difference amplifier and, if required, includes a dedicated sampling and filtering circuit. It features 5-bits trimming and implements curvature compensation through the addition of an integrated resistor with appropriate temperature dependence to the CTAT branch. The proposed bandgap reference circuit was designed in a standard 130-nm CMOS process and was extensively simulated in Cadence Virtuoso, achieving a worst-case 0.756-ppm/degrees C temperature coefficient.
2023
978-1-6654-5109-3
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11571/1488160
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